Design And Implementation Of Mask Wearing Detection System Based On FPGA

In recent years,wearing masks in public places has become the consensus of most countries.At the same time,CNNs have a good application prospect in the field of image recognition.CNNs require a lot of resources and memory,and the amount of calculation is large.FPGAs have become mainstream due to their reconfigurable,lowlatency and low-power consumption characteristics.One of the application platforms.In this paper,the main research results of deploying CNNs on the FPGA side and identifying the wearing of masks are as follows:1.On the software part,the self-designed CNN is used to detect the wearing of masks,the accuracy rate of 98.5% can be obtained,and the situation of irregular wearing of masks and covering of mouth and nose with hands can be distinguished.2.In the hardware transplant aspect of the algorithm,this article innovatively uses a variety of optimization methods to achieve the hierarchical output of convolution and pooling operations.Considering that the convolution operation is the bottleneck of most CNNs,cyclic transformation and parallelism analysis are carried out for the convolution operation,an 8-parallel reconfigurable convolution operation unit based on weight reuse is proposed in PL side.A pipeline and double buffer design are used inside the operation unit in order to improve the computational efficiency.Large convolution operations are analyzed and split in a way of less demand for system read access due to the limited internal resources of FPGA;the pooling operation is divided into horizontal pooling and vertical pooling in the operation unit,the optimized design is carried out on storage space and operation unit;a double buffered independent computing unit is designed in the operation unit of the FC layers;finally,the Softmax operation unit based on CORDIC algorithm is designed.3.On this basis,drive and optimization design is carried out in the PS side to split the convolution operation and reuse the data,and schedule each unit to complete the acceleration work together.Finally,due to the robustness of neural networks,this paper also uses the method of converting 32-bit floating-point numbers into 16-bit dynamic fixed-point numbers to reduce the memory space occupied by the network model,data transmission of the system and the DSP computing resources.4.Finally,it is tested on XCZU3EG-SFVC784-1-I.The clock frequency of the system is 200 MHz.Average multiplier utilization rate of the convolution operation unit reaches 93.37% in the network model designed above.The effective computing power of the accelerated IP is 11.95 GMAC/s,and the energy efficiency ratio is 5.36GMAC/W.The average processing time for a picture is 37.82 ms,the performance is about 4.7 times than I7-8750 H CPU in speed.The loss is 0.25% after comparing with the software result.