Research And Implementation Of Image Feature Extraction Algorithm Based On TTA

The extraction and matching technology based on image feature has been widely used in the fields of object recognition,image retrieval and 3D reconstruction.The high computational complexity of feature extraction algorithms makes it difficult for software-only implementations to meet real-time requirements.The hardware acceleration of feature extraction algorithms is essential for computer vision applications in embedded systems.This thesis concentrates on the hardware acceleration and implementation methods of image feature extraction algorithms.Scale Invariant Feature Transform(SIFT)and Canny edge detection algorithms are selected as research objects.First,through the study of feature extraction algorithms,aiming at the feature that the convolution operation of the Gaussian pyramid step in SIFT algorithm is relatively large,it is proposed to use recursive Gaussian filtering and 5×5 filtering to improve the algorithm.The results show that mixing the two filters can optimize the algorithm between speed and accuracy.Secondly,by dividing the software and hardware of the algorithm,it is proposed to use an Application Specific Instruction Set Processor(ASIP)to implement hardware acceleration.And the specific instruction set has been defined.Based on the specific instruction set,it is designed a Transport Triggered Architecture(TTA)accelerator,which is implemented by a combination of software and hardware to accelerate the feature extraction algorithm.Third,the accelerator is analyzed and optimized on the architecture simulator.According to the characteristics of the algorithm,a number of special functional units including recursive Gaussian filtering,5×5 filtering,and CORDIC are customized to optimize the overall performance of the acceleration.And the physical design of the accelerator is completed in the SMIC40 nm process.Simulation results show that for an image of 320×240 pixel,the acceleration method proposed in this thesis can extract complete SIFT features at 10 fps and Canny features at 57 fps.The physical design results show that the design in this thesis has a higher energy efficiency ratio and area efficiency,and the total efficiency is improved by 4.57 times compared with known designs.This design also retains the flexibility of ASIP and can quickly integrate other feature extraction algorithms,which is expected to be applied to image feature extraction and matching applications.