Design And Research Of Sparse Convolutional Neural Network Accelerator On FPGAs

Deep Convolutional Neural Networks(CNNs)have achieved state-of-the-art performance in a wide range of applications.However,deeper CNN models,which are usually computation consuming,are widely required for complex Artificial Intelligence(AI)tasks.Though recent research progress on network compression such as pruning has emerged as a promising direction to mitigate computational burden,existing accelerators are still prevented from completely utilizing the benefits of leveraging sparsity owing to the irregularity caused by pruning.On the other hand,FieldProgrammable Gate Arrays(FPGAs)have been regarded as a promising hardware platform for CNN inference acceleration.However,most existing FPGA accelerators focus on dense CNN and cannot address the irregularity problem.In this thesis,we firstly analyze the computational parallelism of convolution layer,and propose a sparse wise dataflow to skip the cycles of processing Multiply-andAccumulates(MACs)with zero weights and exploit data statistics to minimize energy through zeros gating to avoid unnecessary computations.The proposed sparse wise dataflow leads to a low bandwidth requirement and a high data sharing.Then we design an FPGA accelerator containing a Vector Generator Module(VGM)which can match the index between sparse weights and input activations according to the proposed dataflow.Finally,we do the design space exploration and find the best configuration of Processing Unit(PU)array on the given FPGA platform.Experimental results demonstrate that our implementation can achieve 476.7 GOP/s,495.4 GOP/s and 244.5 GOP/s performance for Alex Net,VGG-16 and Res Net on Xilinx ZCU102,respectively,which provides 1.5× to 6.7× speedup and 2.0× to 6.0× energy-efficiency over previous CNN FPGA accelerators.