| Tunneling field effect transistor（TFET）is one of the candidates for low-power（LP）devices in the post-Moore era since it can break through the thermal limit of subthreshold swing（SS）（60 m V/dec）.Thereby,continuing to reduce the power supply voltage.The design of a TFET using two-dimensional（2D）material is a promising solution because the thin body of the 2D material implies an excellent gate control,while the smooth surface means that little carrier is trapped during the transport.Among them,group IV chalcogenide compounds are the most promising channel materials due to their combination of the advantages of two-dimensional materials and their non-toxic and stable nature.Previous work has shown that planar Sn S TFET has a lower on-current,while planar Sn Se TFET has a higher leakage current,but two-dimensional Sn S and Sn Se as stable new semiconductor materials are still the most potential channel materials.In this thesis,we theoretically explore the structural optimized strategy for the 2D Sn S and Sn Se TFETs at the sub-10 nm scale using the ab initio quantum transport computations.The research results are as follows:（1）This thesis suggests an homojunction Sn S TFET device structure with a bilayer Sn S as source and monolayer Sn S as channel and drain.An evident improved on Ion is obtained,where the 10-nm-gate-long Sn S homojunction TFET surpass the ITRS LP device.In addition,negative capacitance effect is introduced under the ultra-short gate length of Lg=5～7 nm,to make the Sn S homojunction NCTFET surpass the ITRS LP devices.（2）We optimize the the leakage current Ileak of the Sn Se TFET by a vertically stacked structure at sub-10 nm scale.The Ileak is significantly reduced,reaching～10-5μA/μm,obtaining an Ion of 488μA/μm,where the vertically stacked Sn Se homojunction TFET can serve as a LP device and surpass the ITRS requirement for LP application.The negative capacitance effect is also introduced to make vertically stacked Sn Se homojunction TFET surpass the ITRS LP devices at Lg=5～7 nm. |
