Research On Test Time Optimization For 3D SoC

With the users' increasing demand for SoC functionality,the number of IP cores integrated on SoC increases,too,which leads to the reduction in the reliability of SoC owing to the long internal connection of the SoC.Henceforth,the 3D SoC are born at the right moment to solve the serious problems faced by traditional 2D SoC.The so-called 3D SoC are interconnected vertically between layers with the help of TSV technology.TSV technology realizes the integration in vertical direction,shortens interconnection length,and supports heterogeneous integration,improves the degree of integration.Therefore,the 3D SoC implemented by TSV technology based on vertical interconnection replaces 2D SoC in the development of semiconductor industry.Since the 3D SoC employs the embedded IP core reused technology with very complex testing process and quite high testing cost,it makes the testing the main research content of 3D SoC.Thereinto,the most important solution to the problem of the testing cost of 3D SoC is to minimize its testing time,which is the biggest factor affecting the testing cost.Nowadays,the 3D SoC can be divided into single-tower 3D SoC and multiple-tower 3D SoC according to the stacking type.Therefore,this paper starts its research by focusing on the minimization of testing time of the two types of 3D SoC,and its main work and innovation points are as follows:An approach to minimize the testing time of a single-tower 3D SoC based on the IP core is proposed.The proposed algorithm assumes that all the hard die are used,and each layer of the hard die contains only one IP core,however,test will finally be worked out on it.And by exploring the stacking order of the IP core,the layers of the stacking will be figured out so as to get the minimum testing time of the single-tower 3D SoC.The result of the experiment based on the using of five different dies on ITC'02benchmark circuit shows that,under different TAM bandwidth conditions,the total testing time of single-tower 3D SoC obtained by the proposed algorithm is better than that of the Schedule algorithm.An algorithm to minimize the testing time of multiple-tower 3D SoC based on partial pipelining is proposed.The proposed algorithm comprehensively takes test pins,the number of TSV and testing power consumption into consideration and and uses the bin-packing for test scheduling.While packing,it not only needs to integrate multiple constraints,but as long as any one of the test resource constraints does not satisfy the test of the die to be scheduled,the die test resources that end the test will be released in turn until the die to be scheduled is tested as early as possible.In this way,the partial pipelining of the die and the unfinished test die is realized,so that as many dies as possible are tested in parallel,and the test time is shortened.The experiment results of two different multiple-tower 3D SoC show that,compared with the LBL,TBT,HA and QPSO algorithms,the proposed algorithm reduces the idle time blocks and reduces the total test time significantly.