Research On Acquisition And Tracking Algorithm In BDS-3 B1i Signal And Verification

With the gradual expansion of the service scope of the Beidou-3 system in China,Beidou navigation systems are increasingly used in various complex scenarios such as indoor positioning,field exploration,and earthquake relief.Affected by obstacles,multi-paths,etc.,so that ordinary receivers cannot normally navigate and locate.Strengthening the research on weak signal acquisition and tracking technology is the key to improving the performance of navigation receivers.In this thesis,the research on the acquisition and tracking technology of Beidou-3 satellite signal in the weak environment is carried out.Based on the analysis and comparison of the three basic acquisition algorithms,this thesis proposes an Improved Time Parallel Acquisition(ITPA)algorithm,which can solve the problem of bit reversal in the navigation message type.The accumulation strategy of coherent integration and non-coherent integration solves the problem of signal capture under low SNR.And the ITPA algorithm achieves high-accuracy capture of D2 weak signals in the B1 band of Beidou.Monte Carlo experiments show that,the ITPA algorithm can capture weak Beidou satellite signal for the carrier-to-noise ratio of 27d BHz when the false alarm probability is 10^-3,and the detection probability is greater than or equal to 0.98.In order to track the frequency and code phase captured by the ITPA algorithm with high precision,this thesis adops the structure of the carrier tracking loop auxiliary code tracking loop.And make a detailed analysis of all the discriminators in the tracking loop,and combine the simulation results to select the most suitable identification algorithm.Unitized sign dot product method is adopted as carrier phase discrimination algorithm.Also,unitized cross-product frequency discrimination method is adopted in frequency-locked loop.The unitary coherent dot product power method with a relatively small amount of computation is adopted.At the same time,simulation results show that the tracking stability can be reached in 1500ms,and the Doppler frequency shift error is approximately 10Hz,the code phase error is less than 0.14 chips,and the carrier loop phase error is 14°.Using Verilog language on ISE Design 14.7 Suite platform to design the ITPA algorithm and the tracking loop modules and FPGA simulation was carried out on ISE to verify the correctness of the functions of each module.Finally,using Xilinx's VC707 development kit to on board verification.