Design Of An Improved Gradient Descent Bit Flipping Decoder For LDPC Codes On FPGA

Since Claude E.Shannon published A Mathematical Theory of Communication in 1984,the channel coding technique has experienced a golden age of development.Many different kinds of error correction code came up,such as Hamming code,Golay code,convolutional code,BCH code,Turbo code,LDPC code and Polar code.Low-Density Patiry-Check(LDPC)codes were first proposed by Robert G.Gallager in 1962 in his PhD Thesis at MIT.However,as a result of the comparatively low development of computer science,LDPC codes didn't gain much attention until 1990s.LDPC codes have capacity-approaching error correction performance which makes them popular in communication system.Gradient descent bit flipping(GDBF)algorithm is a kind of hard-decision algorithm,which shows an error corection capability superior to most known BF algorithms.In this thesis,we propose an improved gradient descent bit flipping(IGDBF)algorithm for LDPC codes.Compared to GDBF algorithm,the proposed algorithm reconstruct the composition of energy function,and add a penalty term to help it converge and get rid of the trapping set.Simulations show that the proposed algorithm has good performance and fast convergence rate compared to other BF algorithms in the art of hard-decision decoding.Moreover,based on the global architecture of GDBF decoder,the Thesis has made a complementation of an IGDBF decoder on Xilinx Virtex7 690 FPGA board.The maximum frequency of the decoder is 132.7MHz and the throughput of decoder is 4.1 Gbps.The Thesis also applys the proposed IGDBF algorithm to LDPC decoding scheme as Green Mode.This application can help the whole LDPC decoder more energy efficient and improve the working range of Green Mode.