Design And Automated Testing Of The Chip Verification Platform

In the development of SoC(System on Chip),the design and validation of the Chip are carried out alternately.After the design of the Chip is completed,the wafer can be manufactured and packaged and tested.Unforeseen defects may occur after the fillet is manufactured,which may come from the designer or the manufacturer.Once the flow plates are manufactured,these defective chips cause economic losses.To control the yield of the chip above 80%,a lot of verification work will be done before the chip flow,which will occupy most of the time in the SOC development stage.In order to shorten the development cycle of the chip,the hardware design and software design are carried out in collaboration,and the verifier develops the chip model according to the design outline using a high-level programming language.In order to verify the correctness of the model design,a verification platform is needed to realize the verification of the chip model.Once the design defect is found,the verifier will give immediate feedback and make corresponding modifications.The process is repeated.However,the difficulty lies in that the repeated verification work will produce different verification methods for different verification scenarios,and each scenario needs to redesign the test cases,resulting in low efficiency of chip development and prolonged development cycle.Therefore,it is necessary to design an automated testing mechanism to optimize the whole verification process.This thesis first gives a brief overview of the different stages of chip development verification scenarios,and discusses the different chip verification methods.And design a verification platform of switching chip,which can provide different service procedures including register configuration,test and development according to the different needs of users.A virtual instrument is designed in the test development module of the verification platform,and packets are sent and received by setting different test modes.Using TCL language and API provided by Sbulun,the conversion mechanism between virtual test instrument and Sbulun instrument is designed to realize the data transceiver of virtual instrument in hardware environment.The results show that when a packet capture test is completed,the verification platform can send and receive packets in different scenarios and automate the analysis of test results,which simplifies the conversion process of different verification scenarios for verifiers and realizes the reuse of test scripts.