The Design Of Millimeter Wave Low Noise Amplifier Based On CMOS Process

In recent years,The user's demand for high-speed communication technology is increasing.Because the millimeter wave frequency band has rich frequency band resources and high transmission rate.It has gradually become the development direction of wireless communication systems With the deepening of research.Ka-band as a part of the millimeter wave frequency band has also been extensively investigated.Compared with other compound processes,CMOS process has the advantages of low cost and high integration.And Low noise amplifier is a key component of wireless communication system.Therefore,it is important to research how to design and work in the Ka-band based on CMOS process Low noise amplifiers are of great significance to the development of modern communication systems.First,The development status of low-noise amplifiers in the millimeter wave band at home and abroad was introduced in this thesis.At the same time,the CMOS process was used in the design of low noise amplifiers and passive device capacitors,inductors,baluns,was also introduced and analyzed.After that,the basic theory of low-noise amplifiers was introduced.After that,Based on 65nm CMOS technology two millimeter-wave broadband low-noise amplifiers which work in the millimeter wave frequency band are designed.According to the low noise amplifier theory described above,A broadband low-noise amplifier with an operating frequency of 33?48GHz was designed.It uses a two-stage cascode structure.The noise reduction technology was used to reduces the noise which introduced by the common-gate transistor,And the peak mismatching network was used to improve the gain flatness and expand the bandwidth.According to the test results,the low noise amplifier gain is 19.1±1.5d B,the DC power consumption of the circuit is 24.78m W,the 1d B bandwidth is about 35?45GHz,the 3d B bandwidth is about33?48GHz,and the gain flatness performance is good,in the range of 37?45GHz,the gain is 20.5±0.1d B.the circuit is unconditionally stable,the total area of the layout is 680×440?m~2.However,the noise figure is only a simulation result,and the minimum noise figure is 4.2d B.Due to the tradeoff between the first circuit and the noise matching process,the input reflection performance of the LNA was not ideal.In response to this problem,A low noise amplifier composed of a single ended cascode structure and a differential cascode structure was designed on the basis of the previous circuit.The operating frequency of this low-noise amplifier is 29?44GHz.In order to reduce the influence of parasitic capacitance on stability and gain,capacitance neutralization technology was used.To reduce the layout area,transformer Balun is used for inter stage matching and output matching.In addition,in order to optimize S11,the size of the cascode transistor has been further increased.However,this also causes the deterioration of noise performance.From the obtained simulation results,it can be seen that the DC power consumption of the circuit is 23m W,its gain is 16.5±1.5d B,its 3d B bandwidth is about 29?44GHz,the minimum noise figure is 4.5 d B,the circuit is unconditionally stable,and the total area of the layout is 580×438?m~2.Based on 65nm process,two low noise amplifiers was designed in this thesis.the performance meets the index requirements,Its gain flatness and bandwidth perform well,it has a certain reference function for the design of future low-noise amplifiers.