Real-time Clock Recovery Algorithm For Free-space Optical Communication

Coherent optical communication technology based on digital signal processing has advantages of high channel capacity,high sensitivity and high spectrum efficiency,and has been widely applied in optical fiber communication and free-space optical communication systems.In optical fiber communication,the real-time digital coherent optical communication module has been commercialized,and the real-time free-space optical communication technology based on digital coherent optical communication is also developing rapidly.As a significant step in the digital signal processing of coherent optical communication,the clock recovery algorithm has a major impact on the performance of coherent receiving system.This paper focuses on the real-time clock recovery algorithm in the free-space coherent optical communication system.The main research contents and innovative work are as follows.1)Some researches of the coherent optical communication and the clock recovery algorithm are investigated and analyzed in this paper.The principles of several typical clock recovery algorithms are introduced at the same time.2)An improved routing storage method to improve the clock frequency error tolerance of the Gardner clock recovery algorithm is proposed.The 2.5GBaud real-time QPSK experiment is completed on the Altera Stratix-V 5SGXMA7K2F40C3 FPGA platform.The experimental results show that when the FEC threshold of 2×10-4 in KP4 is adopted,the tolerance of the improved algorithm can reach 325ppm.3)A dynamic proportional gain parameter method is proposed to improve the dynamic range of the Gardner clock recovery algorithm.The algorithm was verified by online experiments in a 2.5GBaud QPSK coherent communication system based on the Altera Stratix-V 5SGXMA7K2F40C3 FPGA platform.The experimental results show that when the FEC threshold of 2×10-4 is adopted,the system receiving sensitivity can be improved from-47dBm of the fixed parameter algorithm to-49.5dBm,and the power jitter frequency tolerance of the clock recovery algorithm can be improved from 100Hz to 1 kHz.4)The 10GBaud real-time QPSK communication transmitting and receiving experiment is completed on the Xilinx Virtex UltraScale+xcvu13p-flga2577-1-e FPGA platform.Taking 2×10-4 as the FEC limit,the sensitivity reaches-42.5dbm and the theoretical limit difference is 5.5dB.