Design And Implementation Of Real-Time Demodulation System Of Simplified Digital Coherent Receiver For Free Space Optical Communication

Free space optical communication(FSOC)has been intensively studied worldwide due to its advantages compared with microwave communication in the field of wireless communication in recent years.Coherent detection has the advantages of high sensitivity,high spectral efficiency,and it supports advanced modulation format.For this reason,it becomes one of the most important technologies in FSOC at present.Simplified digital coherent receiver uses single photodiode to receive signal and realizes coherent detection and demodulation through digital signal processing(DSP)technology.Thus,it has the characteristics of simple structure and low power consumption,and is more suitable for FSOC systems than traditional coherent receiver.This thesis focuses on design and implementation of real-time demodulation system of simplified digital coherent receiver.(1)The system structure and working principle of simplified digital coherent receivers are studied.The algorithm system of real-time demodulation system including functions of optical field reconstruction,timing recovery,frequency offset compensation and phase recovery is designed.The basic algorithm flow of Hilbert Transform(HT)in frequency domain,Gardner algorithm,M^th power method and Viterbi-Viterbi algorithm is given.(2)Aiming at the problem of the limited optical signal-to-noise ratio(OSNR)dynamic range of the currently used Gardner clock recovery algorithm,an improved feedback-type parallel timing recovery algorithm is proposed,the effects of parameters such as loop filter ratio and integral coefficient and the number of parallel processing channels on algorithm performance are analyzed.Combined with optical field reconstruction algorithm and carrier recovery algorithm,the algorithm system of real-time demodulation system is constructed.The simulation results show that the improved timing recovery algorithm has the advantages of low computational complexity and large dynamic range(-3d B?18d B)of OSNR,and it is more suitable for FSOC system than Gardner algorithm.(3)The design and implementation of the real-time demodulation system are completed used parallel pipeline design method based on Xilinx FPGA development board and Vivado:the development of HT module in frequency domain is completed through the overlapping retention design method;the development and performance optimization of the feedback-type parallel timing recovery module are completed through reducing the total delay of feedback loop by the improvement of angle calculation,summation operation,linear interpolation and so on;the development and resource optimization of the carrier recovery module are completed through the method of reuse.Finally,the real-time demodulation of10G Baud quadrature phase shift keying(QPSK)signal is realized based on the simplified digital coherent receiver,which is expected to meet practical application requirements.