Research And Design Of Wideband 6-bit Digital Attenuator

With the rapid development of microwave communication technology,people's requirements for the way and speed of information acquisition are increasing.A higher bandwidth wireless microwave communication system is required to meet the requirements of various applications for working bandwidth.Therefore,ultra-wideband technology has become a research hotspot.As an important part of the transceiver component,the performance of the digital attenuator determines the performance of the entire transceiver component to a certain extent.GaAs pHEMT process is widely used in RF circuit design due to its high electron mobility.In this paper,two wideband six-digit digital attenuators are designed based on the WIN PD25-00 0.25um GaAs pHEMT process.Designed and tested a X-band wideband six-digit digital attenuator based on 0.25um GaAs pHEMT process.Based on the cascade connection of the T-type attenuation structure and the Pi-type attenuation structure,a phase compensation circuit and an amplitude compensation circuit are proposed.The parallel capacitor structure of the attenuation network is used to reduce the additional phase shift and improve the attenuation accuracy,and the small compensation circuit is used to improve the in-band flatness.the structure achieve lower insertion loss and higher attenuation accuracy.The simulation results show that in the range of 8-12GHz,the RMS amplitude error of the digital attenuator is less than 0.4dB,the insertion loss is less than 6dB,the additional phase shift is-6°?6.5°,the input and output return loss is less than-11dB at 10GHz,the input power at the ldB compression point is 29dBm,the chip size is 2.5mm×0.65mm.A C-X band wideband six-digit digital attenuator based on 0.25um GaAs pHEMT process is designed.Two attenuation topology cascaded structures are used to improve the in-band flatness and reduce the chip area.The effect of the cascading sequence of the cascaded network on the performance is analyzed.The appropriate cascaded structure is selected to improve the matching performance of the input and output ports,the capacitor phase is adopted.The compensation circuit reduces the additional phase shift of the attenuator.The simulation results show that in the range of 4-12GHz,the RMS amplitude error of the digital attenuator is less than 0.4dB,the insertion loss is less than 6dR the additional nhase shift is-3.5°?6°,the input and output return loss is less than-11dB at 10GHz.the input power at the 1dB compression point is 22dBm,the chip size is 2.4mm×0.65mm.