Research And Design Of Key Circuits For Wideband RF Receiver Front-end Module

With the rapid development of wireless communication technology,more and more communication standards have been formulated.At the same time,the market is increasingly pursuing the multi-function and small size of wireless communication devices.Therefore,the design of high-performance RF transceiver system compatible with a variety of communication standards has become a challenging task and has been widely researched at home and abroad.Based on the above background,RF front end module(RFFEM)has become the mainstream solution of RF transceiver system because of its high performance and high integration.In addition,with the development of process technology,the silicon on insulator(SOI)CMOS process is becoming more and more mature.Due to its excellent high-frequency performance,low cost and easy integration advantages,SOI CMOS process currently occupies an important position in the design of RFFEM circuit modules.Based on the GF 130nm SOI CMOS process,this thesis conducts related research and design verification for the low noise amplifier(LNA)and SPDT TRX switch of broadband RF receiving front-end module.It suitable for GSM/WCDMA/LTE multi-mode cellular communication.Aiming at the design of broadband LNA,this thesis designs a common source LNA circuit structure using gate compensation inductance.The current multiplexing common source amplifying structure based on resistance common mode negative feedback achieves the target gain under lower power consumption.At the same time,the combination of resistance negative feedback and source follower active negative feedback structure provides greater flexibility for broadband input matching.In addition,the common source amplifying gate introduces a compensation inductor,which effectively alleviates the high-frequency performance deterioration caused by the parasitic capacitance at the input end,realizes gain flattening and further expansion of the frequency band.The designed broadband LNA circuit consumes only 3.3 mW under 1.2 V power supply voltage.The chip area is 0.72 mm2.For post simulation results,the proposed LNA features 0.5 GHz-3 GHz frequency band with a relatively flat voltage gain of 12.7 dB±0.73 dB,the NFmin is 3.04 dB at 2.8 GHz,and the IIP3max is-9.32 dBm at 1.1 GHz.Aiming at the design of SPDT TRX switch,this thesis combines multi-transistor stacking technology and body self-biasing technology to realize a high-performance switch circuit design on SOI CMOS technology.The multi-transistor stacking design of series and parallel branches solves the problem of poor switching power carrying capacity caused by low MOS transistor drain-source breakdown voltage(BVdss).The body self-biased structure of the MOS in the diode connection mode is utilized to realize dynamic self-biasing?The technology effectively improves the insertion loss and linearity performance of the switch and simplifies the controller.The proposed SPDT TRX switch has been taped out and tested.From COB test results:the proposed SPDT TRX switch exhibits an insertion loss of 0.22 dB-0.29 dB,and the isolation is better than 25 dB in the range of 0.5 GHz-3 GHz.At 900 MHz,0.1 dB compression point of 38.3 dBm is demonstrated.Meanwhile,2HD and 3HD are 92 dBc and 79 dBc respectively for 33 dBm input power.