Design Of SD Card Controller Based On AHB Bus

With the rapid development of the integrated circuit nowadays,So C(System on Chip)has become an essential Chip in the market,playing a decisive role in various fieldsrelated to image and video processing.At the same time,as it's common to attach a Secure Digital Card to So Cto save files in forms of video,image and others,the design of an SD Card controller inside So C is necessary to realize the data communication between So C and the SD Card.Based on Advanced High-Performance Bus(AHB)Specifications and SD2.0Specifications,this paper completes the front-end design of the digital circuit of SD controller.The main steps include:Firstly,this thesis introduces the timing and working mode of AHB Specifications and SD2.0 Specifications,which provides a theoretical basis for the subsequent design.Secondly,the RTL(Register Transfer Level)design of the SD controller is carried out with Verilog hardware description language,which mainly includes six modules,like clock management,AHB interface,command transmission,data transmission,FIFO(First in,First Out)and built-in DMA(Direct Memory Access).In the design,in order to improve the efficiency of data transmission and relieve the pressure of CPU(Central Process Unit)and external DMA,the DMA module is built in,adopting the burst mode transmission of address increment by default.Aiming at preventing the system from crashing due to the time-out response of the SD card,the timeout protection function of the command and data is set.In case some unnecessary interrupts disturb CPU continuously and lower work efficiency,the interrupt shielding function is devised.To reduce power consumption,the software and hardware are set to stop the clock function,so the clock can be turned off when there is no need for data transmission.Considering reducing the economic cost of using ATE(Automatic Test Equipment)Test in the future,the built-in Test module of MBIST(Memory Build-in-Self Test)is added to the FIFO,which is an important feature of the design.Meanwhile,the design supports the data reading and writing of single data line and four data lines,and the data transmission of single and multiple blocks.Finally,the RTL level function simulation of the circuit is completed,and the logic synthesis of the design is completed with the TSMC 28 nm standard CMOS process with no timing violation.The post-simulation verification of the output gate-level netlist is carried out.When the operating frequency of AHB bus is 100 MHz,and that ofthe SD card is 0-50 MHz,the design can complete the correct data reading and writing operation.