FPGA Implementation Of Convolutional Neural Network In Speech Recognition

In recent years,deep neural network has attracted increasing attention.Among many deep learning methods,convolutional neural network has good application in speech recognition since it can provide translational invariance in time and space.Currently,CPU or GPU is the main approach to implement convolutional neural network.However,high computing speed and low power consumption cannot be achieved at the same time.Because of the advantages of rich resource,high computing parallelism,low power and portability,FPGA acceleration has aroused more researchers' attention.In this thesis,a 7-layer convolutional neural network of acoustic model used in speech recognition is customized in FPGA.In the aspect of data quantification,the 16-bit fixed data quantization can effectively decrease data storage and reduce bandwidth requirements with guaranteed accuracy.In terms of hardware implementation,the parallelism in the network is analyzed and then a variety of data multiplexing methods are used for speed optimization in convolutional layer.The row of filters is reused horizontally and each row of input map is reused diagonally.The resources is optimized in fully-connected layers.Pipe-line helps to improve the throughput of the system and PCIe is used to transfer data between FPGA and PC.The convolutional neural network realized in this thesis is verified in Intel Arria 10 FPGA.This FPGA programs with 150 MHz frequency and achieves the speed of 159.5GOPS which is twice faster than Tesla K40 GPU.The power consumption is 15.43 W.It achieves 8 times the energy efficiency ratio of the GPU.