FPGA Design And Implementation Of 5G Physical Uplink Shared Channel Interpolation And Filtering

In 5G NR(New Radio),the wireless interface between the terminal and the base station is a completely open interface.The design of the physical layer is the most important part of the 5G system design.Compared to the key performance indicators of 4G,such as peak rate,spectrum efficiency,user experience rate and delay,5G NR has higher and more comprehensive requirements.The research content of this article is about FPGA design and implementation of interpolation and filtering for channel estimation and equalization of the physical uplink shared channel(PUSCH),which is an important part of uplink signals to the physical resource mapping in time-frequency domain.Because the negative impact of the fading characteristics of wireless channel is uncertain,the processing of channel estimation is necessary.The purpose is to estimate the time domain or frequency domain response of the channel,so as to correct and recover the received data.Then the receiver uses the information of the wireless channel obtained by channel estimation to equalize the received signal and recover the estimated value close to the transmitted signal.The research content of this paper is that because the performance of the basic least square method is poor due to the lack of noise reduction,noise suppression is also needed to improve the estimation performance in engineering.Therefore,in this paper,the DFT and CP waveforms are denoised by transform domain interpolation and minimum mean square error filtering.Then the channel estimation results obtained after noise suppression are filtered in time domain to obtain the correlation matrix for calculating the equalization weight,where the equalization weight is used for linear detection to recover the estimated value of the sending signal.This paper focuses on the engineering realization of the algorithm which is about the design and implementation of this part of the function based on FPGA.Tools such as Vivado and Questa Sim are used to complete the development work and the subsequent design verification.The software simulation and hardware test verify that this function can be realized in the system.The innovation of this paper lies in the engineering realization of the algorithm which is using Xilinx's vu9 p chip,and the design which has realized the functions of interpolation and filtering on PUSCH based on FPGA.Besides,it combined with Vivado development platform and a high practical value by using some commonly used IP core,FIFO,RAM and other design patterns in hardware design to improve the reusability and modularization of the project.