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Simulation And Extraction Of Series Resistance In Sub-100nm FD-SOI Mosfets

Posted on:2021-12-06Degree:MasterType:Thesis
Country:ChinaCandidate:J X ChenFull Text:PDF
GTID:2518306122463984Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
The continuous improvement of modern semiconductor technology has greatly promoted the development of the integrated circuits,and the performance requirements of devices are also increasing.With the improvement of technology,the development of devices has been driven from micron level to nanometer level,and the scale of integrated circuits has also been developed from large scale to super large scale.The miniaturization of MOSFET devices reduces the cost of manufacturing devices and improves the integration of the system,but it also brings some factors that affect the performance of devices,such as short channel effect,mobility degradation.Also,in the process of scaling down the device,it is found that the device has gradually shrunk to the physical limit,but it's hard to improve the corresponding device performance.The size of MOSFET devices is getting smaller and smaller,and the channel length is also shrinking.For long channel MOSFET devices,the channel resistance accounts for a relatively high proportion of the total on resistance,and the influence of source-drain series resistance can be ignored in the process of device performance analysis.However,the size of the device is shrinking,the channel length is shorter and shorter,and the proportion of the source drain resistance in the total on resistance is increasing,which can be compared with the channel resistance gradually.Finally,the influence of the source-drain series resistance on the physical performance of the device is more and more significant.In order to better analyze its influence on the device performance,it is necessary to accurately extract the source-drain series resistance of the MOSFET device.In this paper,two different methods of source and drain resistance extraction are proposed for sub-100nm FD-SOI devices.According to the equivalent circuit model of MOSFET devices,we determine that the bulk charge parameter and threshold voltage are the key parameters in the source drain resistance extraction.For the bulk charge parameter,Ortiz Conde method and threshold voltage definition method are used to extract it respectively.The advantages and disadvantages of the two methods are compared.For the threshold voltage,we use linear extrapolation method,constant current method and second derivative method to extract the V_T.The linear extrapolation method takes the linear extrapolation to zero drain current as the V_T;the constant current method takes the gate voltage at a given constant drain current as the threshold voltage;the second derivative method takes the gate voltage corresponding to the maximum value of the second trans-conductance of the drain current as the threshold voltage.In this paper,we use these methods to extract the threshold voltage.Finally we found that the results of different extraction methods are different.For the source-drain series resistance,the channel resistance method and the mobility constant method are used to extract the source and drain resistance.The channel resistance method cannot intersect each other in the extraction process.Therefore,the experimental results show that the channel resistance method is not suitable for the source-drain resistance extraction of short channel MOSFET devices.The constant mobility method can extract the source-drain resistance only through the transfer characteristic curve(I_d-V_g)and output characteristic curve(I_d-V_d)of a single MOSFET device.It is independent of the channel length,channel width,electron mobility and other parameters,and the extraction process is simple and efficient.Finally,we respectively discuss the relationship between source-drain resistance,channel length and gate bias.Finally,the structure of FD SOI device is built by Sentaurus TCAD,and the relationships between series resistance and channel length,buried oxide thickness,source drain doping concentration are analyzed.The thickness of buried oxide layer is mainly related to the parasitic capacitance of source and drain,which can effectively inhibit the short channel effect of the device and improve the physical and electrical properties of the device.The source-drain resistance of the device can be effectively reduced by controlling the source drain doping concentration.The higher the doping concentration is,the smaller the source-drain series resistance is.
Keywords/Search Tags:Series Resistance, FD SOI MOSFET, Threshold Voltage, Sentaurus TCAD, Mobility Constant Method
PDF Full Text Request
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