Formation Mechanism Of Solder Voids In Power Chips And The Effects Of Voids On Interconnect Reliability

With the rapid development of microelectronic technology,the integration density,signal speed,and power density of chips are also increasing.Due to the requirements of heat dissipation and grounding,the power chip needs to be connected to the substrate or the heat sink through soldering.However,due to the evaporation of solvent flux and air entrainment during the soldering process,voids are often generated in the solder layer.Problems such as poor heat dissipation,stress concentration,poor thermomechanical performance,and reduced reliability caused by these voids have attracted widespread attention in the industry.This research is aimed at solder voids in power chip packaging structures.The motion behavior of bubbles in liquid solder and the effects of voids on interconnect reliability are studied.The specific research results are as follows:A gas-liquid two-phase flow model of bubbles and liquid solder was established.The motion behavior of bubbles in liquid solder under different parameters was investigated.The material and process parameters affecting bubble escape were analyzed.It was found that the vacuum can basically remove the voids in the solder layer.In addition,reducing the contact angle of the liquid solder,increasing the flatness of the soldered surface,and using a sufficient amount of solder can effectively promote the escape of air bubbles,thereby reducing the void ratio of the solder layer.The simulation results were fitted by X-Ray testing the void ratio of the reflow samples with different parameters.It was found that in the experiment,the vacuum can realize the ultra-low void ratio below 1%.The use of alloy solder with better wettability,reflow under a nitrogen protective atmosphere,and an increase in the amount of solder can effectively suppress the solder layer voids.In addition,the pressure applied during the reflow process will promote the side overflow of the solder,but the larger pressure will cause excessive solder overflow and increase the void ratio.X-Ray test results show that the effect of process parameters on the formation of voids is consistent with the simulation results.A finite element model of power chip / DBC substrate interconnections containing voids with different parameters was established.The effects of different void sizes,locations,and distributions on interconnection reliability were studied.It is found that large-sized voids will seriously reduce the reliability of the interconnection,and the effect is not significant when the void ratio is less than 10%.The harm of corner voids and edge voids is greater than that of the center voids.When the voids are dispersedly distributed,their impact on reliability often depends on some voids on the edges,because these voids intersect with the solder layer edges to form geometric sharp corners,and these sharp corners will cause rapid accumulation of damage.