Study On Preparation And Characteristics Of Low-power Two-dimensional InSe Transistor

In recent years,with the down scaling of transistors,the increasing short channel effect makes the speed and power consumption of silicon-based devices approach the physical limit.Therefore,it is necessary to find new channel materials to meet the requirements of future integrated circuits with low power consumption and high performance.The 2D material is considered as a potential channel material with the characteristics of atomic level thickness,flatness and excellent electrical properties.Among the two-dimensional materials,indium selenide(InSe)with high mobility at room temperature and indium triselenide(?-In₂Se₃)with two-dimensional ferroelectricity have become research hotspots.This article focuses on the preparation and analysis of low-power InSe field effect transistors(FETs)and the application of?-In₂Se₃ferroelectricity.The specific research content results are as follows:1.A variety of characterization techniques are used to establish the method for determining the number of layers of InSe thin films.The variation of material properties such as Raman spectrum,surface potential,and electrical conductivity with thickness are revealed.The 2D InSe thin film with controllable number of layers is prepared by a micro mechanical exfoliation.For the first time,an InSe thickness comparison color card is obtained by combining high-resolution optical metallographic microscope and atomic force microscope(AFM)to realize rapid and reliable thickness identification of the film.Resonance Raman,XRD and TEM characterization methods have proved that the InSe used is?phase.The Raman results show that the peak strength of A₂"-LO(200 cm^-1)can be used as an important reference index for determining the number of InSe layers by testing the films with different thicknesses.The conductive AFM(CAFM)test proves that there is interlayer resistance between the films.Kelvin probe force microscope(KPFM)reveals the trend of increasing surface potential(work function)as the number of thin film layers decreases,which provides theoretical support for the selection of appropriate metal and material to achieve good ohmic contact.2.Low-power InSe FET with SS as low as 89.2 m V/dec is prepared by the traditional photolithography process.The analysis of electrical properties reveal that the surface charge density of the dielectric layer is the key factor affecting SS.Firstly,through the treatment of the surface of the substrate material and the study of the dielectric material,combined with the law of KPFM's research on the surface potential of the material,the InSe material with appropriate thickness is selected to achieve a good ohmic contact with the metal electrode.We first prepared an InSe back-gate FET using a 300nm Si O₂ dielectric layer.The FET exhibits a high current on/off ratio of 2.75×10⁶,and the carrier mobility reaches 184 cm² V^-1s^-1.The multilayer InSe back-gated FET exhibits a low SS of 406 m V/dec,and V_th is reduced-7.67 V.In order to further improve the device performance,we have deposited 15 nm Al₂O₃gate dielectric with ozone as the oxygen source,although the device mobility is only 20.1cm² V^-1s^-1,the SS of the prepared InSe FET is still reduced to 89.2 m V/dec,which is the smallest SS among the currently reported InSe FETs,and the V_th is reduced to-0.356 V.Through a systematic analysis of electrical performance,it is proved that the low SS of Al₂O₃ gate dielectric devices is mainly due to the lower trap charge density on the surface of the dielectric layer,and the main influencing factor of low mobility is surface polar phonon scattering(SPP).Compared with the current research progress,the low power consumption index of our device is currently the lowest reported.This study explores the use of InSe FETs for low-power electronic applications.3.Based on the negative capacitance and charge storage properties of the ferroelectric gate stack,combined with the transfer electrode process,InSe NCFET and enhancement-mode FET are fabricated for the first time.The minimum SS of the device is 19.3 m V/dec,and the V_th is drifting to 0.92V.Firstly,the InSe NCFET with a 2/15 nm Al₂O₃/HZO ferroelectric gate stack was prepared using a transfer electrode process.The minimum SS was 58 m V/dec,which breaks the thermal electron limit at room temperature.Secondly,by optimizing the HZO thickness of the ferroelectric layer and changing the 2/15 nm Al₂O₃/HZO ferroelectric gate stack to a 2/20 nm combination,the minimum SS of the device was reduced to 31.4m V/dec,and the average SS is less than 60 m V/dec for over three decades of drain current.The switching ratio of the device is 1×10⁶,and the threshold voltage V_th is reduced to-0.74V.The experimental results prove the correctness of the optimization scheme.At the same time,the analysis of the hysteresis voltage,SS,and|V_th|with V_DS analysis prove the uniqueness of the back gate NCFET structure.Finally,using the principle of ferroelectric gate stack charge storage,pulse voltage bias is performed on the optimized device to realize the storage of electrons,and then the enhancement InSe FET is obtained.After+4 V pulse voltage bias for 1s,V_th moves to 0.28 V forward,SS_{for min} reduced to 29.4 m V/dec.When+4V pulse voltage was biased for 10s,V_th increases to 0.92 V,and SS_{for min}=19.3 m V/dec and SS_{rev min}=26.6 m V/dec.The experimental results show that the application of ferroelectric gate stack can realize ultra-low power consumption enhanced InSe FET.4.For the first time,the ferroelectricity of?-In₂Se₃ is used to prepare?-In₂Se₃/Mo S₂ferroelectric heterojunctions.Firstly,the ferroelectricity of?-In₂Se₃ is analyzed from the crystal structure by the destruction of the center of symmetry of the crystal structure.The TEM and Raman spectroscopy have proved that the In₂Se₃ is an?phase with the misaligned center of the crystal structure.Secondly,the PFM test results not only show the coexistence of out-of-plane and in-plane piezoelectricity in the?-In₂Se₃ film at room temperature,but also prove that the formation of ferroelectric domains is not directly related to the thickness of the sample with the change of the number of layer.Then the CAFM was used to prove that the?-In₂Se₃/Mo S₂ heterojunction with the switching ratio larger than 100 has stable and reversible non-volatile resistive switching characteristics.The I-V curve shows electrical hysteresis.This method offers the possibility to quickly and stably analyze the performance of ferroelectric heterojunctions.Finally,resistance switching effects have also been observed in actual heterojunction devices fabricated using transfer electrode technology.The results show that 2D?-In₂Se₃ and Mo S₂ have great application potential for realizing non-volatile information storage devices.