A Study Of Modeling And Priority Scheduling Of High Bandwidth Memory

X-DSP is a high-performance multi-core accelerator developed by Microelectronics Institute of National University of Defense Technology.The accelerator is expected to integrate dozens of CPU cores and hundreds of GPDSP(General Purpose Digital Signal Processor)cores to enhance its parallel computing capabilities.However,with the continuous development of accelerator design technology,storage bandwidth is becoming a determinant of accelerator performance.High-bandwidth memory(HBM),as a kind of memory with ultra-high bandwidth supply capability,has great potential to become the mainstream storage technology for next-generation microprocessor design,especially high-performance microprocessor design.Therefore,the X-DSP project plans to use HBM as its main storage device.However,because the real HBM IP is too large,if the real HBM IP is used in the verification of other system-level components of the accelerator,the initialization alone will take about half an hour.If the reading and writing of data is performed several times,it may even take several days to complete the operation.This loss of time will undoubtedly have a huge impact on the normal progress of the X-DSP project.For the above problems,a virtual model of memory can be established and used as a substitute for real memory to accelerate system-level verification.Many scholars at home and abroad have conducted research on memory modeling for their own needs.Yuan et al.designed a hybrid analysis DRAM performance model that uses memory address tracking to predict the DRAM efficiency of the DRAM system when this memory scheduling strategy is used.This model is mainly used to analyze the performance of the memory.Shen Pengcheng and others designed a multi-channel DDR controller model,which uses a transaction-level modeling method.A counter-based spontaneous memory access scheduling algorithm is used to achieve considerable memory access efficiency with a small system resource overhead.The establishment of this model aims to optimize the performance of the memory.And this article aims at accelerating system-level verification and accelerating the progress of the project,and proposes a design method of HBM IP virtual read-write model.This method first analyzes the structure and function of HBM IP,understands the operation mode of HBM IP and its initialization method.And on the basis of fully understanding the HBM reading and writing functions required by the system,the HBM IP component-level verification platform was built.The verification platform consists of a master model that automatically issues effective incentives,an HBM IP as the device under test,and an HBM IP read-write model that includes a comparator and a reporter.Then,by modifying the master model,various incentives were issued to test and understand the functional characteristics of HBM IP in various scenarios.During this period,the functions of the HBM IP read-write model need to be continuously modified.Finally,a read-write model that can work normally in various scenarios is obtained,and then modifies the interface of the model to implement a virtual read-write model that can be run in place of real HBM IP in system-level verification.In addition,in order to make X-DSP get higher performance,this thesis also proposes two design methods of buffer scheduling module that supports priority scheduling.This method draws the conclusion that the buffer scheduling module should adopt a distributed architecture in the accelerator system by analyzing several important components connected to the HBM IP in the system.Then through a top-down design idea,a static buffer priority scheduling module composed of synchronous FIFO buffers was first designed,and its various function points were verified through the component-level verification platform to achieve correct function of buffer scheduling Module.Afterwards,based on the idea of linked lists in the software,a special buffer component containing 4variable depth sub-FIFOs was designed.The component is used to form a buffer,and a dynamic buffer priority scheduling module is implemented.Finally,through component-level verification,the functional correctness of the design is confirmed.Through top-down design ideas and HBM IP component-level verification,this thesis implements a virtual read-write model for replacing real HBM IP in system-level verification.By implementing this model,the functional characteristics of HBM IP can be understood more deeply and can learn the latest memory technology.By using this model,it can facilitate the verification of other modules at the system level,accelerate the speed of X-DSP system-level verification,and accelerate the progress of the overall project.In addition,this paper also designs and implements a static buffer priority scheduling module and a dynamic buffer priority scheduling module for buffer scheduling of read and write HBM IP requests from different cores.Through component-level verification and coverage analysis,the functions of each module are fully verified.As the final statement coverage,branch coverage and toggle coverage of the component-level verification of the two modules have reached 100%.It is believed that the functions of the two buffer scheduling modules have been correctly implemented.That is,these modules can buffer the access requests of different DSP cores and CPU cores to HBM IP,and prioritize high-priority requests according to the priority value.