Design Of Low-voltage Power Line Broadband Carrier Communication System And Its FPGA Implementation

Power Line Communication(PLC)as a data transmission technology,utilizes existing power networks.With the advantages of wide coverage,low cost,stable operation,PLC is widely used in indoor communication,mining communication and so on.However,this technology meets its bottleneck due to the uncertainty of the PLC channel.Orthogonal Frequency Division Multiplexing(OFDM)is introduced to solve the problem and it can not only achieve parallel transmission of signals but also have good anti-interference characteristics.Many foreign PLC standards organizations have begun the research on PLC protocol based on OFDM technology.Currently,State Grid of China has also released a new version of lowvoltage broadband PLC technology standard protocols based on OFDM technology.Based on this standard,this paper focus on the research and improvement of the key technology of the physical layer in PLC system and gives a hardware design scheme with FPGA.The main contributions of this paper are summarized as follows:1.We introduced the principle of the OFDM system and the data frame format of the Low voltage broadband PLC technical specification physical layer protocol.And the overall design scheme of the PLC system is given.2.The two commonly used synchronization algorithms are analyzed in detail and their performance is analyzed through simulation.Considering the implementation difficulty and synchronization performance of FPGA,the local cross-correlation algorithm is improved.The improved algorithm reduces the amount of calculation and its performance meets the actual system requirements.3.Analyzing delayed cross-correlation frequency offset estimation algorithm.The algorithm is improved based on the preamble structure of this system and the FPGA hardware implementation.Simulation results show that the estimation performance is improved with extended preamble.4.Least Square(LS)algorithm is analyzed and improved based on the leading structure of actual system.The mean square error simulation results show that the performance of the improved algorithm is improved.5.Soft Input Soft Output(SISO)algorithm is introduced.The principle of the MAP algorithm and its four commonly used algorithms as well as two turbo decoding decision methods are analyzed.The method of cyclic state is optimized while the overall structure of the decoder remains unchanged.In order to reduce the delay of hardware resource utilization and calculation,this paper utilizes sliding-window algorithm to improve the decoder algorithm.The MATLAB simulation results is used to select the parameters of the improved Turbo decoding algorithm.The final simulation results show that the algorithm meets the actual system requirements.6.The FPGA scheme of the key technology of the PLC physical layer is designed in this paper.We simplify the complex interleaving method in the transmitting module.The function of each module is verified by hardware simulation.Turbo decoding timing simulation shows that decoding delay is reduced after adding sliding window.