Study On CMOS Based Quantization System For PET Scintillation Pulse

Positron Emission Tomography(PET)is the most advanced imaging system in the field of medical imaging.All-digital signal processing is an important direction for the development of PET systems.Accurate sampling and quantification of high-speed scintillation pulse signals is a key technology of all-digital PET systems.An accurate working clock is an important prerequisite for all-digital PET stabilization.In this paper,based on the latest development of CMOS integrated circuit design technology,a low-power,highly-integrated discrete threshold comparator that satisfies the high-speed sampling of scintillation pulses and a system clock oscillator that suppresses the fluctuation of the operating voltage are designed.It lays the foundation for integration with high-performance all-digital PET systems.According to the characteristics of the PET scintillation pulse signal,a Discrete Threshold Comparator(DTC)chip and a high-speed quantification system based on this comparator were designed using TSMC-0.18 ?m CMOS technology.The experimental results show that the threshold of the DTC comparator can be adjusted from 229 m V to 1426 m V and the propagation delay is less than 1.5 ns.Based on DTC comparator,two circuits of system-level FLASH-ADC and chip-level DTC-ADC are designed.The test results show that the system-level FLASH-ADC based on the DTC comparator can achieve a sampling rate of 600 MS/s.The DTC-ADC has been verified by simulations to achieve a sampling rate of 1 GS/s at a bandwidth of 32 MHz.In order to obtain a stable system clock,a fully integrated OSC chip that effectively suppresses voltage fluctuations was designed using TSMC-0.18 ?m CMOS process.Through oscillation detection and low-dropout linear voltage regulation technology,the purpose of the oscillator to start up quickly and reduce power consumption is achieved.By designing the internal bandgap reference and current bias of the chip,the interference of the power supply fluctuation to the chip performance is reduced.The simulation results show that the phase noise of the output signal of the chip is-124.986 d Bc/Hz@1 k Hz and the start-up time is less than 1 ms under the conditions of 2.5 V?3.6 V operating voltage and-40°C?120°C temperature.The chip size is 1130 ?m × 730 ?m.The test results show that the chip can oscillate at2.2 V?3.3 V operating voltage and-45°C?90°C temperature,and the power consumption is less than 13.2 mW at 3.3 V.