FPGA-based Highway Vehicle Target Radar Echo Simulator

In the process of radar development,how to debug efficiently is a key problem to be considered.Using radar echo simulator can generate virtual target with range,speed and angle information,and simulate the actual environment to add noise with controllable signal-to-noise ratio,so as to shorten the research and development cycle and reduce the development cost.How to transmit the data to the signal processing board accurately and high speed when there are many transmission channels in the radar echo simulator is also a problem to be considered.CSI-2 interface technology is a good solution.According to the above discussion,this paper designs and implements a multi array radar declination echo simulator based on FPGA.According to the target parameter information set by the user,the system generates 64 array vehicle target de skew echo signal and transmits it to the signal processing board through CSI-2 communication interface.This paper mainly carried out the following work:1)The system scheme design and simulation are completed.First,the task requirements and parameters are analyzed,and then the overall logical structure and system workflow are designed.Then,the mathematical model of target de skew echo signal is established,and the flow of signal generation and verification is given.The flow is simulated and verified by MATLAB program.2)The hardware circuit of the system is designed.Through the analysis of five different angles,the model of FPGA chip is determined.Combined with the notes of schematic drawing,the power circuit,clock circuit,network interface circuit,CSI-2 interface circuit and FMC interface are designed.3)The 64 array multi-target de skew echo signal module is implemented.The design idea of modularization is adopted,and six sub modules are designed.Based on the idea of FSM,a multi-target de skew echo signal is designed,which can switch between multiple waveform types in order.By using the idea of time-division multiplexing,multiple parallel target signals can be transmitted in time-sharing on the same link,thus saving more than three times of multiplier resources when adding the phase information of array elements.4)The CSI-2 protocol stack based on FPGA is implemented.The design idea of modularization is adopted,and three modules are designed.For the protocol encapsulation module,the function of adding long packet header and parameter field and reserving CRC position is completed based on FSM by using three-level register delay input data.For the data rearrangement module,the functions of data distribution,package composition and CRC calculation are completed.For the transmission module,FIFO is used to solve the cross clock domain problem between the input data side and d-phy side.The finite state machine is used to add the corresponding short packets according to the timing requirements and send them to the signal processing board through D-PHY.In this paper,a multi array high-speed vehicle radar de skew echo simulator based on FPGA is designed.After verification and test,the function of signal generation and high-speed transmission is basically completed.