The Design Of High-speed Low-jitter Clock Buffer And Linear Regulator

In today’s digital era,the operating frequency of digital circuit systems is increasing,and the system requires a high-performance clock signal to provide reference timing,so clocks with high speed,low jitter and low inter-channel skew are urgently required.Aiming at these requirements,a clock buffer with four in-phase outputs is implemented on the 180 nm Bi CMOS process.The buffer has superior noise performance and driving ability,and its maximum operating frequency is 4GHz.In addition,to reduce the jitter caused by the unstable supply voltage,this thesis also design an auxiliary LDO chip to supply the clock buffer.With the characteristics of high stability and strong driving ability,the LDO can meet the power supply requirements of the clock buffer.For the clock buffer chip,its main performance parameters are introduced in detail.The conversion relationship between jitter and phase noise is summarized.In order to achieve a maximum operating frequency of 4GHz,bipolar transistors are used as the input stage of the LVPECL interface in this thesis.The circuit adopts a differential input structure to effectively reduce the common mode noise.At the same time,low jitter performance of the clock buffer is achieved through noise analysis and parameter optimization of the circuit components,adding the common-mode level buffer and layout noise isolation,and low inter-channel skew is achieved through layout parasitic optimization and proper placement.Then the circuit design and post-layout simulation are completed,under the condition of 3.3V supply voltage and typical corner,the gain of the input LVEPCL interface is 17.07 d B and GBW is 18.95 GHz,the gain of the output stage is 19.70 d B and GBW is 25.45 GHz,the additional jitter of the clock buffer is43.71fs（@12k～20MHz）.The duty cycle distortion,propagation delay and inter-channel skew are meet the specifications.When the input signal swing is 300 m V and the frequency is 4GHz,the measurement results show that the inter-channel skew is 5.3ps,the propagation delay is 256.6ps,and the rising time is 60.7ps,the falling time is 56.9ps.For the LDO chip,this thesis proposes the specifications of the LDO circuit according to its requirement of supplying the clock buffer.This thesis focuses on analyzing the stability of the circuit under heavy current load and using the Damping Factor Control（DFC）frequency compensation technology to compensate the loop,finally,the circuit design and post-layout simulation are completed.The simulation results of DC characteristics show that the minimum voltage drop of the LDO is 150 m V,the average quiescent current is 32.5u A,and the maximum load current is 160 m A.Without adding large-area compensation capacitors,the simulation results of AC characteristics show that the loop phase margin is 9.29° before adding the DFC circuit and 64.7° after adding the DFC circuit.The simulation results prove the superiority of DFC technology in frequency compensation.