Low Jitter Broadband Clock Synthesis Module Design

High-end systems in today's communications field require clock signals with extremely low noise and integrity.Jitter is an important time domain parameter of clock signal,and phase noise is its frequency domain equivalent.And modern instruments for broadband clock demand is also increasing.Therefore,the study of broadband low jitter clock generator has important practical significance.This article revolves around wideband low jitter clock synthesis module study design,combining indicators clock synthesis scheme was designed,on this basis to realize the hardware circuit output,after the debugging and testing,reached 50kHz-4GHz broadband,the resolution of 5 Digits,less than 1 ps of clock jitter indicators,including the output phase noise of frequency 1600MHZ-98dBC/Hz@10kHz.The main contents are as follows:1.Theoretical research on clock jitter: firstly,the definition and common classification of jitter are expounded,and then the conversion relationship between jitter and phase noise is derived,which provides a theoretical basis for frequency domain testing and analysis of jitter.2.Synthesis scheme design of low-dither broadband clock: According to the requirements of the subject index,on the one hand,combining with the subject index to compare several frequency synthesis technologies,design the synthesis scheme of broadband high-resolution clock by DDS driven PLL;On the other hand,combining with the phase noise model of PLL,the noise model and its characteristics are discussed,focusing on the effect of loop bandwidth on the output noise of PLL,the jitter attenuation scheme of double PLL is designed.Finally,the design scheme of broadband low dither clock synthesis circuit with DDS excitation dual PLL is obtained.3.Design and implementation of clock synthesis module: Analyze clock indexes and assign phase noise indexes to guide chip selection.The constant temperature crystal oscillator is used to provide a reference clock with high stability and low bottom noise.AD9954 is selected to realize the resolution index required by the system and its out-of-band filter is designed.The performance index of Si9392 evaluation board is tested,and its structure principle,shaking out link and output configuration are described.ADF4356 is selected to realize frequency doubling and loop filter is designed.Finally,phase noise performance is simulated.ARJ20A4 H is selected as a switching device to solve the high frequency band output switching problem.The control module is designed,and the logic and driver program are designed by using MCU+FPGA.The voltage and current required by the chip are calculated,and DC/DC+LDO is adopted to provide the current and voltage to the chip.Finally,PCB layout is designed and the output of hardware circuit is realized.4.System debugging and testing: the debugging methods of each module of the system are described.On this basis,the testing methods of jitter in time domain and frequency domain are analyzed.Then the random jitter,resolution and frequency accuracy indexes of the clock are tested,and the test results are analyzed.5.Summary and Prospect: Summarize the research and work content of the full text,and based on the experience in the research process of the project,put forward the problems and directions that can be improved.