Analyzing And Hardening Single-Event Transients For The Clock Distribution Network In Nanometer CMOS Integrated Circuits

As the core of various spacecraft electronic systems,anti-radiation integrated circuits(ICs)have become the key to supporting the spacecraft.The rapid development of the aerospace industry has made the spacecraft put forward higher performance and anti-radiation requirements for its core devices and circuits.The traditional manufacturing process cannot meet the needs of the space application.At present,the anti-radiation IC with high processing capacity is mainly based on the nanometer process nodes.As scaling continues,the node capacitance is reduced,the supply voltage is reduced,and the circuit operation speed is increased.These all increase the vulnerability of the IC to single event transient(SET).SET has become one of the bottleneck problems in the radiation hardening of modern high-frequency ICs.Clock is the most important signal in any synchronous design.Distributing most widely on the chip,the clock signal usually must travel the longest distance and operate at the highest speed.There is a probability that an abnormal behavior in the whole system will be generated if the clock signal is altered by radiation effects.It has been shown that clock distribution networks(CDNs)are becoming increasingly vulnerable to transient faults known as SET owing to technology scaling down.In the deep sub-micrometer regime,the CDN contributes significantly to the chip-level soft error rate(SER).Upsets occurring in the CDN have the potential to dominate the chip-level SER if no mitigation techniques are applied.This paper studies the SET sensitivity analysis,evaluation,measurement,and hardening techniques for the CDN in nanometer technology.The main works and contributions of this dissertation are as follows:(1)In this paper,a novel SET susceptibility analysis and evaluation methodology for CDN in any circuit is proposed.This methodology allows a more precise analysis of SET propagation in the CDN and the CDN-SET-induced incorrect latching by electrical simulations of circuits working in real time.In our simulations,injection location of the SET traverses all clock nodes on the CDN,injection time of the SET is random,and pulse width of the SET is random in a certain range.This can reflect more realistically and accurately how an IC works in the aerospace.(2)The influence of different sequential elements(D-flip-flops and D-latches,the two most commonly used sequential elements in modern synchronous digital systems)on the SET susceptibility of the CDN was quantitatively studied.Trigger modes of sequential logic elements vary with their types.Therefore,whether an SET on the CDN will induce incorrect data latching of the sequential element and how long the incorrect latching will last vary with the sequential element type.That is to say,type of the sequential element has a great influence on the SET susceptibility of the CDN.Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based design.(3)Frequency dependence of the SET susceptibility for CDNs is quantitatively studied.With the continuous increase of the clock frequency,the gap between pulse widths of SETs occurring on the CDN and the clock cycle is getting smaller and smaller.Thus,the number of effective SET on the CDN and the number of incorrect data latching due to SETs on the CDN increase with the clock frequency.This paper quantifies the effect of clock frequency on the CDN SET susceptibility in the DFFbased design in the rage of 1 MHz to 3 GHz.A large number of simulation results show that,as the IC operation frequency increases,the probability of an effective SET being captured at the clock input of the sequential element and the probability that it causes an incorrect latching increase significantly.(4)This paper proposes an on-chip relative susceptibility test circuit(OC-RSTC).For the first time,OC-RSTC realized the measurement of relative SET/SEU sensitivity of each node in any circuit.Due to that OC-RSTC can measure the relative susceptibility of an IC when it works in real time,the measurement results can reflect truthfully and accurately how an IC works after radiation in the application.According to the measured relative SET/SEU sensitivity of each node and the anti-radiation target expected to achieve,designers can harden their ICs selectively and partially,drastically reducing overhead while guaranteeing quantified anti-radiation performance.(5)A novel SET mitigation technique for the CDN is proposed,in which the clock inverter is redesigned with dual inputs and dual outputs.Based on this kind of dual-in-and-dual-out(DIDO)inverter,the hardened CDN of a case study circuit was designed and evaluated.Both the post-layout simulations and heavy ion radiation experiments show that,compared with the unhardened CDN,the probability capturing SET at the leaf nodes of the hardened CDN is significantly reduced.The area,performance,and power overheads introduced by this mitigation technique are negligible.Moreover,the SET mitigation technique is easy to realize and can be used in the CDNs with different topologies.This paper finally concludes all the main research works,and describes the corresponding results and achievements of each work.It also points out the theoretical significance and practical value of these research works for high-reliability IC design.At the same time,it introduced the related works which need to make further improvement and in-depth research in the future.