The Design Of Backplane Of Arbitrary Waveform Generator With 10GSPS Sampling Rate

Arbitrary Waveform Generator（AWG）,as a common signal source in measuring instruments,which can be used to generate waveform signals with high bandwidth,high frequency resolution and variable phase.In the modern testing field,the requirements for the storage depth and the number of channels of arbitrary waveform generator are gradually increasing.It is necessary to provide high speed data bus and mass memory for each channel.As a result,the scale of device of waveform synthesizer module are multiplying,that the domestic chip integration and the design of instrument structure are difficult to meet the requirements of high storage depth and multi-channel simultaneously.To solve this problem,based on the 10 GSPS arbitrary waveform generator project,designed a multifunctional backplane with bus expansion,clock generation,channel synchronization and other functions in this paper.To complete the design of eight-channel of arbitrary waveform generator with 10 GSPS through the‘Backplane and Modules’ structure.The main work contents are as follows:1.Conduct a holistic analysis of the project and divide the functions.Based on the design structure of arbitrary waveform generator,compare the characteristics of instruments with different structures.The combination of ‘Backplane and Modules’ is adopted as the design structure of this project.Then,the function of ‘Backplane and Modules’ is divided.Each two channels were designed as a waveform synthesizer module to give full play to the performance of dual-channel high-speed DAC.In the backplane,aiming at the problem of insufficient number of upper computer bus,the bus expansion function is designed to ensure that each channel can independently output waveform signals.Aiming at the synchronization problem of multi-channel,the clock generation function and trigger conditioning function are designed to provide synchronous clock and synchronous trigger signal for each waveform synthesizer module.2.The overall scheme design of backplane.According to the functions of backplane,complete the corresponding scheme design.According to the storage depth requirements of 2G sample points/channels of the project,PCIe 2.0×4 bus is used as the bus of the project.And the output bus of the upper computer is expanded through PCIe Switch,which is respectively supplied to backplane and four waveform synthesizers.The clock source is extended by clock fan out and clock distributor to meet the clock synchronization requirements of JESD204 B link,DAC,FPGA and other devices in each waveform synthesizer module.And divide the scheme of clock synthesis across modules.High resolution DAC and high speed comparator was used to adjust the external trigger signal to meet the requirements of 0.1V resolution and-1.25V～+1.25 V amplitude range.Due to the bus enumeration function of the upper computer,it is necessary to power the backplane and each waveform synthesizer module before the upper computer,and realize the time-sharing power on of each module and the standby function of the instrument through the power switch circuit.3.The design and implementation of hardware circuit of backplane.Select the key components and design the specific hardware circuit according to the requirements of the indicators in each scheme of backplane.Complete peripheral circuit design of PCIe Switch,and verify bus expansion function.According to the device manual,complete the design of impedance matching of clock and trigger circuit,and verify the chip output level standards;Complete the design of power circuit and power switch circuit of backplane;Evaluate the delay of PCB board level wiring,and make the time delay of transmission line between waveform synthesizers modules within 10 ps.Finally,test the hardware circuit of backplane.According to the test results,the backplane can accurately send the waveform data and control commands of the upper computer to each module.The synchronization precision of the clock signal provided by the backplane for each module is 200 ps,and the synchronization precision of the trigger signal is 40 ps.