Research And Design Of LDO With High PSRR And Low Noise

The fast-developing integrated circuit industry puts forward higher requirements for power management chips.The traditional single power supply can no longer meet the power requirements of highly integrated chips.Therefore,the integrated circuit neutron module circuit needs a certain voltage range.Some circuits sensitive to power noise,such as PLL,radio frequency circuit,clock generation circuit,high-speed DAC circuit,these circuits all need a low noise power module,to ensure the normal realization of the circuit function.Since RF and microwave electronic products work in a wide frequency band,they need a power supply that can provide low noise and still have a higher PSRR in the high frequency band.Therefore,it is very meaningful to study and design an LDO with higher PSRR and low output noise in the high frequency band.This thesis analyzes the noise distribution of the traditional LDO.For the noise from bandgap reference,an optimized low-pass filter is introduced at the output to reduce the chip area while ensuring noise suppression,and the PSRR of LDO circuit is also improved.The source-level negative feedback structure is used for the noise from the error amplifier,In order to reduce the equivalent input noise.after a detailed analysis of the power ripple transmission path of the traditional LDO,based on a feed-forward ripple cancellation(FFRC)technology,a PSRR enhancement circuit is added between the drain and the gate of the power transistor,which realizes the function of copying the fluctuation of the drain ripple to the gate of the power transistor in an equal amount,avoiding the influence of power supply ripple on the power transistor VGS,which improving the PSRR of the LDO.at the same time,the consistency of high PRSS in the entire simulation frequency range is achieved;the conventional ESR resistor is connected in series with a large capacitor to ensure the stability of the system;finally the layout design and simulation verification are completed.This work is based on SMIC0.13μm CMOS process to complete the design of the circuit.The results show that the LDO can provide an output voltage of 2.8V and a load current of1μA～50m A.The PSRR in the low frequency band is 82 d B,and the PSRR at 1MHz is 57 d B.The PSRR in the entire simulated frequency range is maintained above 38 d B.Compared with the LDO without the FFRC circuit,the PSRR at low frequency and high frequency(1MHz)Increased by 12 d B and 10 d B respectively.In the frequency range of 10Hz～100KHz,the output integrated noise is 15.31μVrms.The phase margin of the system is more than 50°in the range of 1μA～50m A load current.After the layout is completed.the post-simulation of the whole circuit is down.The results show that the PSRR is 82 d B at low frequency band,52 d B at 1MHz,and the output integral noise is 15.45μVrms.