Design Of A Fully Integrated Switched Capacitor DC-DC With Light Load And Low Ripple

Microcontrollers applied to wireless sensor nodes of the Internet of Things often work in the sleep mode.In the sleep state,the chip uses a low-leakage voltage conversion circuit to supply power to reduce chip power consumption.Compared with low-dropout linear regulators and inductive voltage converters,switched capacitor DC-DC has the characteristics of low cost,high integration,and high efficiency at light load.It is suitable for sleep scenarios,however,the output ripple of the switched capacitor DC-DC of the traditional structure is large,and the efficiency drops sharply when the load current is reduced.In order to improve the power efficiency of the chip in the sleep state,it is necessary to design a fully integrated switched capacitor DC-DC with light load,high efficiency and low ripple.The multi-phase clock cross-drive scheme will reduce the ripple and cause a driving loss that is a multiple of the number of clock phases.In order to improve the conversion efficiency of the fully integrated switched capacitor DC-DC,the clock phase is reduced to two,and load adaptation Bias linear regulators is increased to further reduce ripple.It is proposed to increase the structure of the NMOS master-slave power tube and the bias circuit in the linear regulator,and copy the 1/N of the load current as the feedback current to control the circuit loss and reduce the static power consumption of the overall circuit.The feedback current controls the output frequency of the oscillator and serves as the bias current of the linear regulator,and adaptively adjusts the power consumption of the control circuit and the linear regulator according to the load current.Finally,in order to further reduce the static power consumption,a self-powered circuit based on the power supply switching module is designed.After the output voltage is stable,the power supply of the oscillator and part of the clock processing module is switched to the output voltage.The fully integrated switched capacitor DC-DC is based on the TSMC 40 nm process design,and uses a total of 240 p F on-chip capacitors.The layout area is 0.093mm2.The circuit layout simulation results show that the FF process angle and 80℃ are the worst case.At this time: the load range is 50 n A～5u A,output voltage 700 m V,the output voltage ripple is less than 10 m V in the full load range;at 50 n A,200 n A,500 n A,5u A load,the conversion efficiency is 30.7%,51.67%,59.43% and 62%,the results reached the expected index.