Fully Integrated CMOS LDO Linear Regulator Design

Low dropout linear regulator (LDO) as the power management chip (PMU) is animportant circuit module and integrated heavily into the on-chip system (SOC), a digitalchip, high-performance analog to digital/digital to analog conversion chip. For digital/analog mixed SOC, the digital circuit interference on analog circuits increase, so analogcircuits and digital circuits need a separate power supply is applied to reduceinterference between digital and analog mixed and brought to dynamically adjust powerconsumption. Furthermore, fully integrated LDO linear regulator came into being. Fullyintegrated LDO linear regulator can be used as a separate sub-module system powersupply, with power supply noise suppression, reduce interference, while eliminating theadvantages of the introduction of a bonding wire inductance transient pulses, in additioncan also reduce chip devices and chip pin, so fully integrated LDO linear regulator tobecome an integral part of system on chip integrated circuit modules.In this paper, CSMC CMOS0.5μm process, the use of Cadence IC5141Tools forthe proposed fully integrated LDO linear buck regulator design, Sub-modules whichinclude: bandgap reference voltage, reference current source, an error amplifier,transient response enhancement circuit, power management, the feedback resistornetwork, Fully integrated LDO overall simulation,that input voltage range3.2V~6.0V,the maximum output voltage3.013V minimum3.004V, the load current0~350mA,load capacitance0~100pF, quiescent current maximum63.52μA, power supplyrejection ratio≥61.63dB. Load regulation of0.0003%,0.08%line regulation.