| With the continuous development of aerospace electronic systems,the highly integrated task management computer(WMMC)as the brain is being upgraded,and various sensors such as eye,ear,mouth,foot,hand and nose,weapon suspension systems,etc.are all advancing with the times.,The amount of signal information generated is increasing day by day,and the avionics bus as the nervous system also needs to be upgraded.Under this premise,the need to adapt to the airborne environment such as improving the bus bandwidth,transmission rate,reliability,reducing time delay,anti-interference,reducing costs,and reducing the overall weight of the bus network becomes urgent.This thesis takes the research and implementation of high-speed avionics bus node based on 1553 B as the topic,and combines the advantages of traditional MIL-STD-1553B((Military Standard,Digital Internal Time Division Command/Response Multiplex Data Bus))protocol and Fibre Channel(Fibre Channel)protocol to design a bus interface module that supports10Mbps/20 Mbps with adjustable transmission rate.(QBUS module as high speed BUS module),while supporting BC/RT/BM function software adjustable,etc.This greatly improves the transmission rate of the traditional 1553 B protocol bus and adapts to the needs of the times.This thesis has completed the hardware design of the avionics bus node,including the selection of the development board model.Here,the A7 product of Xilinx,the 9054 chip of the bridge chip PCI,and the power clock are selected.Then there is the design of logic modules,including BC control module,RT control module,BM module,data interface module with upper application,time management module,Flash storage module,codec module,data transceiver module,etc.Then there is software design including PC application software(used for design mid-term inspection),host application,host driver,etc.Finally,the debugging results and analysis. |
