Design And Implementation Of High-speed Data Transmission For Phased Array Ultrasonic

Phased array ultrasonic testing is an important industrial nondestructive testing method.The hardware system generally consists of the ultrasonic transmitting circuit,the ultrasonic receiving circuit,the data buffer circuit and the FPGA circuit.Because of its many parallel data conversion channels,FPGA needs to receive a large amount of data from the ultrasonic receiving circuit.Compared with the parallel interface,the JESD204 B interface can effectively reduce the size of the PCB.The thesis designs a 64 * 64 phased array ultrasonic flaw detection board based on JESD204 B interface and completes the design of the digital control module of the high-speed data transmission system.A 64-channel phased array ultrasonic hardware circuit based on JESD204 B interface is designed for nondestructive testing application.It includes a 64-channel ultrasonic receiving circuit,a clock distribution network circuit,a DDR2 circuit and a power distribution network circuit.Signal integrity simulation was carried out on the DDR2 circuit and JESD204 B physical layer circuit.For the DDR2 circuit,it has been verified through the pre-layout simulation that the parallel termination can reduce signal reflection for address bus signals effectively.The post-layout simulation further confirmed that the DDR2 signals meet the signal integrity requirements.The layout and wiring constraints for the JESD204 B physical layer circuit was determined through pre-layout simulation.The post-layout simulation shows the insertion loss of the JESD204 B physical layer link is only-1.5d B at 6GHz and the JESD204 B physical layer performance meets the requirements.Finally,the digital control framework is implemented based on FPGA.The designs of JESD204 B IP module,ultrasonic receiving circuit configuration module and clock distribution network circuit configuration module are also completed.For the 64 * 64 phased array ultrasonic flaw detection board,the S parameters of the JESD204 B physical layer link were measured.The test results were consistent with the simulation.After the clock distribution network was configured successfully,the output waveforms of the clocks were measured.The measured results meet the design requirements.The timing also was verified for the JESD204 B IP module,clock distribution network configuration module and ultrasonic receiving circuit configuration module.The JESD204 B IP module can work stably when the link transmission speed reaches 6Gbps.The designed JESD204 B IP used 70% less resource when compared with the Xilinx JESD204 B IP.The result shows that the designed phased array ultrasonic board meet all the design target and provided a feasible technical route for the miniaturization of industrial phased array ultrasound instruments.