Research On Spaceborne Dynamic Load Cache Scheduling And Management Technology Based On DDR3

Nowadays,space exploration and ground monitoring are important tasks of satellites.As the number of single missions of satellites increases,the detection equipment carried by them also increases.These devices will generate a huge amount of data.There are intricate data interactions between devices,and the bit rate of part of the payload data is getting higher and higher.Therefore,how to flexibly buffer and transfer high-speed dynamic payloads so that the satellites are limited Bandwidth and working hours,the transmission of important information is particularly critical.Based on this background,this article relies on the "FPGA design of XX multi-load and high-dynamic on-board routing system" project,and launches a series of researches on the design requirements of high-speed multi-load reception,dynamic buffer scheduling,and fast transfer of the project.,High-speed dynamic cache scheduling and cache space management are the core research content of this article.This article focuses on the current mainstream solution applied to the on-board routing system-DDR3 SDRAM cache array,and mainly studies and deals with the following issues: 1)How to realize the cache scheduling of dynamic load data with as few cache chips as possible?An improved WRR scheduling algorithm is proposed.In the initial state,the initial priority is set for each queue,and a fixed weight is configured for each priority queue.During the transmission process,it is based on the current buffer amount of each priority queue and the The load code rate corresponding to the queue jointly determines the priority of the queue,and finally the buffer is polled in turn according to the priority of the queue.When the load code rate changes,the priority of each load data corresponding queue will be recalculated to determine the polling order,which ensures the rationality of the priority setting of each queue,and effectively solves the high data buffer delay of each queue when the number of queues is large.The problem.2)With limited storage space,how to manage the cache space of each load data while ensuring high usage? Due to the dynamic change of the load code rate,the space occupied by each load cannot be estimated,and the method of pre-allocating the buffer space is not applicable,and further detailed management of the buffer space is required.After calculating a reasonable basic cache unit capacity,the basic cache unit address of each load and its cached data type and other information are stored in the BAT table to achieve efficient management while ensuring the utilization of cache space.This paper realizes load buffer scheduling and buffer space management with FPGA as the main control,and complies with the CCSDS protocol to frame and encode data without hindering the high-speed transmission of data.The above designs have been subjected to RTL simulation and FPGA board-level verification to ensure the accuracy and feasibility of the design.