Fabrication And Performance Reserch Of MoS₂ Negative Capacitance Field-effect Transistors

In this century,MOS integrated circuits have developed tremendously depending on"Moore’s Law".However,MOS devices have almost reached the scaling limit of their physical size.At the same time as the size of MOSFET is scaled,how to reduce the operating voltage of the MOSFET to reduce power consumption is particularly important.However,for conventional gate dielectric materials,the Boltzmann limit based on the Boltzmann distribution defines the 60 m V/dec subthreshold swing limit of the MOSFET at room temperature,and it is difficult to continue to reduce it.How to break through the sub-threshold swing limit of silicon-based MOSFETs and reduce device power consumption has become the key to field-effect transistor research.Therefore,this thesis has important practical application value for the research on how to reduce the power consumption of the device.First,this thesis introduces two methods for preparing two-dimensional material MoS₂film samples,namely micromechanical peeling method and chemical vapor deposition method.Among them,the size of the sample prepared by the micromechanical peeling method reached more than 70μm,which laid a good foundation for the subsequent preparation and experimental work of related devices.Second,Based on the preparation of MoS₂ film samples by the micromechanical peeling method,this thesis also prepared a field-effect transistor based on silicon/silicon dioxide as the substrate and MoS₂as the channel and tested its electrical performance.The test results It shows that the device has good electrical properties,in which the metal electrode has a good ohmic contact with the two-dimensional material,which lays the foundation for the subsequent contact between the metal electrode and the multilayer material.Finally,this thesis uses graphene as the gate electrode and CIPS as the gate negative capacitance layer to prepare a four-layer two-dimensional material of graphene/CIPS/h-BN/MoS₂a new type of MoS₂negative capacitance field effect transistor with a stacked structure.The influence of the thickness of the negative capacitance material CIPS on the performance of MoS₂negative capacitance field effect transistors was explored,and the reasonable capacitance matching plays an important role in the negative capacitance effect.The prepared MoS₂negative capacitance field-effect transistor exhibits a steep subthreshold swing and a large current-on-off ratio.The minimum subthreshold swings of the forward voltage and reverse voltage sweeps have reached SSmin=37.5 m V/dec,SSmin=36.7 m V/dec,which breaks through the traditional sub-threshold swing limit and reduces the power consumption of the device.At the same time,the current-on-off ratio reached the order of 10⁷,and the off-state current reached the order of 10^-13.In addition,the effects of annealing and light on the performance of MoS₂negative capacitance field effect transistors are also explored.After thermal annealing at 200℃in vacuum for 2 hours,the hysteresis window of the device is significantly reduced.The minimum hysteresis window is 0.05V,which can be ignored.In addition,the MoS₂negative capacitance field effect transistor has a steep sub-threshold swing,which helps increase the ratio of light to dark current,and has potential application prospects in the field of optoelectronic applications.