Investigation On Parasitic Capacitance Of 14nm FinFET Technology

With the semiconductor technology scaling down,the density of metal interconnects continues to increase,and the circuit delay caused by the parasitic capacitance and resistance accounts for an increasing proportion of the total circuit delay.As the process complexity increases,the accuracy and reliability of parasitic capacitance extraction at 28 nm technology nodes and beyond are getting worse.At the 14 nm technology node,due to the process deviation caused by the use of Fin FieldEffect Transistor(Fin FET)and double patterning technology,the factors affecting the parasitic capacitance of integrated circuits have become more complicated.In order to obtain the parasitic capacitance accurately and consequently obtain a more accurate and complete description of the parasitic parameters,this dissertation mainly does the following works: First,based on the basic concept of parasitic capacitance,simulation theory,and measurement methods,the dissertation qualitatively discusses the impact of new technologies of 14 nm process on the parasitic capacitance.Secondly,based on the analytic results,a reasonable simulation scheme is designed.The high-precision 3D capacitance simulation and finite difference method are used to simulate the interconnect parasitic capacitance,and the impact of the 14 nm process on the intra-layer capacitance,inter-layer capacitance,and the process corner is quantitatively analyzed.Finally,according to the results of the simulation,the layout of the capacitance test structure is designed in order to obtain the actual capacitance deviation after tape-out,thereby obtaining a more accurate and complete description of the parasitic capacitance parameters.