Research On ESD Protection Devices With Low Trigger Voltage

With the continuous development of advanced semiconductor manufacturing technology,Electrostatic Discharge(ESD)has gradually become a major threat to the reliability of integrated circuits,so the research on effective and appropriate ESD protection technology has become one of the urgent tasks for researchers.The difficulty of effective ESD protection is that the reduction in the size of the transistor requires the device to have a smaller ESD protection window while maintaining a certain robustness.This article first introduces conventional ESD protection principles,and then discusses typical ESD protection methods in more detail.On this basis,this paper focuses on the working principle and existing problems of SCR-LDMOS during ESD protection,and has taken the following targeted improvement measures:(1)Aiming at the problem that the trigger voltage is too high and the sustain voltage is too low in the traditional SCR-LDMOS structure,which causes the ESD protection window to be too large,a new type of embedded dual MOS triggering SCR-LDMOS structure is designed in this paper.The new structure introduces PMOS and NMOS structures at the anode and cathode ends respectively,and connects the drain ends of the two MOS structures through wires.On the one hand,the new structure transfers the avalanche breakdown point from the traditional P-body/N-epi junction interface to the P+/N-buffer and P-body/N+ junction interface,thereby reducing the trigger voltage of the device;on the other hand,the newly introduced PMOS-NMOS current path provides an additional discharge channel for minority carriers,and uses the shunt principle to reduce the injection of hole and electron currents into the N-type epitaxial layer and the P-type body region,and effectively suppress the conductance modulation effect inside the device.The device holding voltage is increased,and the voltage clamping speed is also accelerated.The device simulation software compares the traditional and new structures with the same area under the same conditions.The results show that the ESD protection characteristics of the new structures have been greatly improved.Specifically,the trigger voltage has been reduced by 61.93% and the holding voltage has been increased.By more than 3 times,the failure current is reduced by 15.52%.Therefore,the new structure is achieving a greater improvement in the ESD window,while the device maintains a certain degree of robustness.(2)This paper further proposes and designs a structure with embedded double N+ regions.The new structure embeds an N+ zone in the N-epi layer and the P-body zone respectively and connects the two through wires.The new structure adds a PN junction-NPN1 transistor current path between the anode terminal and the cathode terminal.On the one hand,the new structure uses a diode as the trigger unit to assist in opening the new NPN1 transistor discharge current,reducing the trigger voltage of the device;on the other hand,the newly introduced PN junction-NPN transistor current path can provide additional hole and electron current path,reducing their injection into the N-epi layer and P-body area,can effectively suppress the conductance modulation effect inside the device,increase the device's holding voltage,and speed up the voltage clamping speed.In addition,as the new structure introduces a new current path,the robustness of the device is also improved.The device simulation software compares the traditional and new structures with the same area under the same conditions.The results show that the ESD protection characteristics of the new structures have been greatly improved.Specifically,the trigger voltage is reduced by 49.83% and the holding voltage is increased.By more than 4 times,the failure current has increased by 30.16%.Therefore,the new structure improves the robustness of the device while achieving a greater improvement in the ESD window.