| Technology scaling along with power and thermal limitations ushers the industry to the many-core system era. Thread level parallelism and complex applications demand a communication architecture that can provide high bandwidth communication and facilitate efficient usage of the computational units. Therefore, the communication architecture plays a major role in the performance of applications and the energy expended on data movements. The communication framework can be viewed at: 1) the interconnect infrastructure (physical) level and, 2) the inter-thread communication (logical) level. This thesis offers three different approaches to address the communication issues in many-core systems at the physical and the logical levels. First, we propose a novel low-power all-optical Networks-on-Chip (NoC) with a deterministic wavelength routing algorithm. This routing algorithm is based on wavelength division multiplexing that allows us to reduce the number of wavelengths and optimize micro-ring resonators in optical switches. The key advantages of our optical network are simplicity and lower power consumption. Second, to improve performance of on-chip interconnect infrastructure, we employ three-dimensional (3D) integration technology. To tackle the temperature issues in 3D NoCs, we model the mapping problem as an Integer Linear Programing (ILP) problem and propose three static ILP-based thermal-aware mapping algorithms. We then investigate the thermal constraints and their effects on temperature and performance. Third, we propose a new scheme to dynamically predict the critical path of a multi-threaded application. We formulate the cache statistics and the barrier arrival times as a machine learning problem to predict critical threads. We propagate criticality of these critical threads to the other threads using lock contention information. This dissertation demonstrates how opportunities at the physical and logical levels can be used to improve the communication framework. |
