FPGA Implementation of Iterative Soft-Decision Decoder for the (127,119) Reed-Solomon Cod

Reed-Solomon (RS) codes are commonly used in the digital communication field due to their strong error correcting capabilities. In this thesis, a hardware architecture is proposed for the iterative soft-decision decoding of RS codes of prime lengths. The proposed GFT-RS-LDPC decoder is implemented on a Xilinx Virtex-7 FPGA for RS(127,119) code. The decoder has a moderate complexity and can be used for practical applications. The performance of the implemented GFT-RS-LDPC decoder was verified by comparing it with a fixed point and floating point model in MATLAB. Several optimizations to the architecture have been proposed to reduce the decoding latency and to increase the throughput upto 2.4 Gbps.