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Synthesis, Testing and Tolerance in Reversible Logi

Posted on:2019-04-23Degree:Ph.DType:Thesis
University:University of Lethbridge (Canada)Candidate:Nashiry, Asif MdFull Text:PDF
GTID:2478390017493956Subject:Computer Science
Abstract/Summary:
In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits.
Keywords/Search Tags:Reversible, Thesis, Voter circuit, SWAP and fredkin
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