Novel architectures and synthesis methods for high capacity field programmable devices

Field Programmable Devices (FPDs) are rapidly gaining popularity for implementing digital circuits due to their attractive features such as reprogrammability and fast time to market. This thesis proposes two new architectures, called the Hybrid Field Programmable Architecture (HFPA) and the Computational Field Programmable Architecture (CFPA).;The HFPA represents a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LUTs, and Complex Programmable Logic Devices based on PLA-like blocks. The methodology used for development of this new architecture is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The HFPA is evaluated by technology mapping a set of circuits into the new architecture and estimating the total chip area needed and the depth for each circuit, compared to the area and depth that would be required if only LUTs were available. Using the technology mapping algorithms, we partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. We present results for a number of mapping trade-offs to evaluate the benefits of the HFPA. Our experimental results indicate that LUT-based FPGAs need 11% more chip area and 65% higher depth than the HFPA. Another mapping trade-off, which minimizes the area of the circuits, shows that the area and depth benefits of the proposed architecture over traditional FPGAs are 25% and 21%, respectively.;This thesis also considers a more aggressive step to improve the area-efficiency of FPDs by focusing on a special class of applications. In this dissertation, the CFPA is introduced that is targeted at compute-intensive applications. These applications are important because of their use in the expanding markets in data processing. We explain the logic resources in the CFPA and a synthesis method with which we have mapped a number of circuits to the new architecture. According to our results, the computational architecture is more area-efficient than general-purpose FPGAs by a factor of 2.8 times for the benchmark circuits that are considered.