Low cost, adaptive, fault tolerant routing in low dimension direct interconnection network

Throughput and latency are critical parameters in multiprocessor interconnection networks. These parameters are governed by the combination of routing node and interconnect performance. Recent years have seen several new interconnect technologies reach the stage of maturity where they may be applied in practical systems. One such technology is free-space optical interconnect. The problems of wiring density, low data-rates and limited integrated circuit (IC) pin-out are neatly side-stepped by the use of optical interconnect. In order to make practical use of optical interconnects, packet routing node data rates must increase by an order of magnitude or more. At the same time, latency cannot be sacrificed as it is critical to the performance of multi-processor systems. One possible avenue to meeting the required performance is to re-examine the hardware cost of packet router architectures and attempt to improve them. The research presented in this thesis attempts to do exactly that. The result of this research is a packet router architecture known as the Cellular Router. The router allows massive throughput, while maintaining low latency. The architecture is designed to minimise silicon area and maximise achievable clock rate in any given fabrication process. The router is scalable, in the sense that area requirements increase linearly along one axis in proportion to increased throughput. This thesis describes a novel packet router architecture. It is a compact, power efficient, scalable design that is capable of exceptionally high throughput. The Cellular Router allows the benefits of free-space optical interconnects to be effectively utilised in multi-processor systems.