Research On Optical Interconnects For New Memory Technologies

As a national strategic high-tech technology,high-performance computing is an important technique to solve a series of challenging issues such as national security,economic development,and technological progress.High-performance computing is developing rapidly with the goal of tens of billions of floating-point operations per second."Big data" and "Big computing" are typical characteristics of high-performance computing.The memory system is an important part of the high-performance computing system.The increasing gap between computing and memory access capability makes the "memory wall" problem a bottleneck restricting the overall performance of the system.As the main memory,the traditional dynamic random access memory(DRAM)has the advantages of fast read and write speed,mature technology,and long service life.However,with the continuous development and refinement of on-chip processes,DRAM has reached a bottleneck in terms of capacity density,bandwidth,latency,scalability,and energy consumption.The new three-dimensional DRAM memory modules such as Hybrid Memory Cube(HMC),High Bandwidth Memory(HBM),etc.have the advantages of large memory capacity and high bandwidth.The new non-volatile memory modules such as Phase Change Memory(PCM),Resistive Random Access Memory(RRAM),etc.have the advantages of non-volatile data,high memory density,low static power consumption and radiation resistance.The novel memory technology has become a research hotspot for solving DRAM bottlenecks.The interconnection architecture between the memory system and the on-chip multi-core computing system is a bridge of memory access communication,and is a key factor affecting the performance of high-performance computing systems.Traditional electronic interconnection architectures cannot meet the needs of many-core computing systems for future computing-intensive and data-intensive applications in terms of parallelism,energy efficiency,and adaptability.Optical interconnect technology has the advantages of high parallelism,high energy efficiency,etc.It has become a promising candidate for future computing systems.This thesis aims to design the interconnection network for memory access communication with new memory technologies.The characteristics from of high-performance computing application level and device level are investigated.Combined with the characteristics of three-dimensional memory modules and non-volatile memory modules,the efficient interconnection networks for on-chip multi-core computing system are designed.The appropriate memory module is selected for different applications.The high-bandwidth,lowlatency,low-power topology and new memory access communication strategies are designed.The memory access interface suitable for the interconnection architecture is designed,and the memory access power consumption,crosstalk and other performance are optimized according to the memory access calculation model.Through network simulation and hardware prototype verification,the performance of the scheme is evaluated,and the interconnection network design goals of high parallelism,high scalability and high adaptability are achieved.The main research contributions are briefly described as follows:(1)To solve the problems of low parallelism,poor scalability,and high power consumption of the on-chip interconnection networks,a high-performance optical interconnect architecture for on-chip multi-core systems is designed.By studying the distribution and expansion of processor cores in the network,the distribution of optical waveguides and micro-rings in the optical network is optimized.Combined with the allocation and multiplexing of wavelength resources,based on the interconnection structure between on-chip processor cores and between processor cores and memory modules,a dynamic separation,and reconfiguration of interconnection structures is proposed.Comprehensively consider the power consumption characteristics of various on-chip optical devices and electrical devices,build a device-level power consumption model and a network-level power consumption model,and effectively reduce the power consumption and energy consumption of the optical interconnection network through the power consumption model.(2)According to the memory access traffic characteristics and memory system requirements of high performance computing,a new memory access interconnection network architecture for HPC applications is proposed.Based on HMC,HBM and other three-dimensional structural characteristics and organization forms of memory,a scalable on-chip interconnection network architecture is proposed with high memory access parallelism and high memory access bandwidth.It has been proved to reduce the interaction of memory access requests of different cores in the network.The energy distribution mechanism,laser source layout method and laser source power optimization strategy in the optical interconnect topology between the cores and memory modules are proposed to reduce the dynamic power consumption of on-chip multi-core operation.Two interconnection network architecture expansion methods are proposed to ensure high parallelism,low power consumption,and low crosstalk performance of interconnection network while expanding system computing resources and memory resources.(3)Based on the requirements of on-chip and off-chip memory for different applications in high-performance computing and the characteristics of data,this thesis proposes a new hybrid memory interconnection network architecture.Through the hybrid memory characteristics and hybrid memory forms,combined with the high-performance computing application traffic characteristic model and memory access model,a high-parallel,lowpower,self-adaptive network topology architecture between computing nodes and hybrid memory modules is proposed,as well as the network topology wavelength allocation scheme.(4)By constructing an interconnection network simulation system for distributed memory,the performance and advantages of the proposed interconnection structure,switching unit and memory access communication scheme are verified in terms of communication latency,bandwidth and energy consumption.Combined with application requirements and data flow characteristics,the configuration method of network parameters and network load in the simulation platform is improved,and the performance advantages of the proposed interconnection network are verified based on PARSEC instance tests.and the performance advantages of the proposed intelligent network are verified through example tests.Through silicon-based optical tape and testing optical switching unit,the functional verification of the optical switching unit is carried out,and the optical insertion loss,optical signal-to-noise ratio and other performances of the optical switching unit are analyzed.By establishing single-wavelength and multi-wavelength crosstalk noise models,and comparing the optical interconnect structures with the same conditions,the advantages of the proposed highperformance optical interconnect structure in terms of crosstalk noise and optical signal-tonoise ratio are verified.