An ASIC implementation of a multicast message routing switch for interprocessor communications

A novel hardware based multicasting message routing switch has been developed for use in interprocessor communications networks. The importance of interprocessor communications in the design of computer architectures has increased rapidly over the past 10 years with the advent of multicomputers and parallel processing systems in general. This has encouraged research into a diverse range of methods for interconnecting processors. Hardware message routing devices are now widely used as an efficient and scaleable means of interconnecting processors in multicomputers. A review of 'state of the art' hardware routing based communications has been carried out, and coupled with experience of previous research in this area, a design specification was produced for a routing switch. The design incorporates a number of original features including: hardware based multicast message support, split channel link operation, access to an internal control port from any link and error recovery. The design was initially captured in VHDL (Vhsic Hardware Description Language) and then simulated to confirm the specified functionality. A four link prototype design was then synthesised using Field Programmable Gate Array libraries and verified using static timing analysis. The prototype design has been tested on a development board at link speeds of 11 Mbit/s. Waveforms from the development board were captured on a logic analyzer and are presented to highlight a number of important results. Performance evaluations have been carried out and possible areas for future enhancement are described. This design methodology has facilitated the creation of a reusable core of Intellectual Property which can be customised to specific end user requirements in terms of functionality and target technology.