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Wavelet and entropy coding accelerators for JPEG2000

Posted on:2002-07-10Degree:Ph.DType:Thesis
University:Arizona State UniversityCandidate:Andra, Kishore VenkataFull Text:PDF
GTID:2468390011995278Subject:Engineering
Abstract/Summary:
The upcoming image compression standard, Joint Photo Expert Group's JPEG2000, has a feature set tuned for diverse data dissemination. Support of the feature set is possible due to adaptation of Discrete Wavelet Transform (DWT), Bit Plane Coding (BPC) and Binary Arithmetic Coding (BAC). In this thesis, a system level architecture to perform the JPEG2000 compression scheme is proposed. The architecture consists of accelerators for DWT, BPC and BAC along with interfacing memories and a global controller. It has been implemented in Very high speed integrated circuit Hardware Description Language (VHDL). The estimated area in 0.18 μ technology is 3 mm and estimated frequency of operation is 200 Mhz.; The DWT accelerator implements the transform using a lifting-based scheme. The architecture consists of a processor, a memory module and a control block. It is meant for applications where a fast subband data generation is not required, as in JPEG2000. Precision analysis study has shown that, with 5 levels of wavelet decomposition, 16 bits of precision is required for lossless/near lossless performance. A high-performance architecture suitable for time-driven compression schemes has also been proposed. The architecture consists of four processors, two memory modules and local controllers. This architecture generates two subband coefficients every cycle.; The BPC accelerator operates on the wavelet coefficients, along the bit planes, to generate a context and data bit pair using the Embedded Block Coding with Optimized Truncation algorithm. Specialized registers have been designed to handle the state information bits required for the algorithm and to reduce the memory accesses.; The BAC accelerator operates on context and data bit pair, generated by BPC, using the MQ coder algorithm. The proposed architecture consists of special purpose registers, two memory blocks and a controller. By-pass mode has been used to speed up encoding by 15% and decoding by 25%.; To further speed up BAC, a new methodology that codes multiple bits contained in a non-overlapping window is proposed. This method reduces the number of computations by 60%–70% at the expense of a slight reduction in compression ratio compared to the Q coder. The drawback of this methodology is that the bit stream generated is not compatible with the JPEG2000 bit stream.
Keywords/Search Tags:JPEG2000, BAC, Wavelet, Coding, Bit, Architecture consists, Accelerator, Data
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