Statistical modeling of MOSFET devices, circuits, and interconnects for improving manufacturability of integrated circuit design

There are always uncontrollable fluctuations in semiconductor manufacturing process. As semiconductor technology being aggressively scaled down today, circuit performances are expected to be increasingly sensitive to manufacturing variations. Thus, design for manufacturability (DFM) and yield optimization should be integrated into IC design. This thesis investigated three areas important for improving manufacturability of IC designs.; In the first part, a new statistical modeling approach was developed based on the routinely collected parametric data. Statistical information of these parametric data was captured using Principal Component Analysis, and then efficiently represented using an advance sampling technique, Latin Hypercube Sampling technique. An algorithm was suggested to effectively extract SPICE models from these sampled parametric data. The obtained SPICE models, which contain statistical information of the process, are useful for estimating and ensuring certain production parametric yield of a design before it is sent to mass production.; In the second part, a current mismatch model of MOS transistors was derived from BSIM3v3 SPICE model. The model is accurate in a wide range of MOS transistors down to submicron. When the output of a circuit functional block is mainly determined by the balancing between a pair of critical transistors, the developed mismatch can be applied to predict the variation of output due to mismatch between these two transistors under different design parameters and operational conditions.; The third part of the research is about searching for optimum interconnects designs that both meet the performance specification and are robust with respect to process variations. A formal design procedure has been demonstrated based on TCAD simulation and combined array design of experiments. Evenly spaced Pareto optima or tradeoff points are obtained using a multiobjective optimization technique, known as Normal Boundary Intersection (NBI) algorithm. Designers can then select desired designs from the Pareto curve without using arbitrary weighting parameters. The proposed DFM procedure was applied to the 0.12μm CMOS technology, and optimization results were discussed and verified using Monte Carlo simulation.