AID: An interactive debugger for high-level synthesis that uses dependence flow graphs as the intermediate representation

Validating and verifying a design is a very important aspect of the embedded systems design cycle. This allows errors to be located early in the design process. Simulation tools have been used to validate designs at the algorithmic as well as the register-transfer level (RTL); however, these tools do not relate events at the RTL level to the source-code (VHDL) statements that gave rise to them during the synthesis process.; We present an interactive debugger for high-level synthesis to relate the design specification written in behavioral VHDL to the parallelized flowgraph intermediate representation that is executable and simulatable. The intermediate representation contains the processing information to map source-level constructs to RTL-level constructs during high-level synthesis. This work is part of the project to develop a verified high-level synthesis system that produces a register-transfer-level design from a behavioral specification.; We discuss the implementation of the interactive debugger component of the proposed high-level synthesis system that relates the design specification written in behavioral VHDL to the parallelized flowgraph intermediate representation. This component consists of three sub-components which will be discussed. Finally, we discuss additional functionality and extensions that could be made to the interactive debugger.