| Over the last few years, the wireless market has experienced an exponential growth. To sustain this growth, along with the increasing demands of new wireless standards, the cost, battery-lifetime, and performance of wireless devices must be enhanced.; With the advancement of radio frequency (RF) technology and the requirement for more integration, new RF wireless architectures are needed. One of the most critical blocks in a wireless transceiver is the frequency synthesizer. It significantly affects all three dimensions of a wireless transceiver design: cost, battery-lifetime, and performance. In this thesis, we present new RF synthesizer architectures with low-power consumption, high-performance, and low cost.; The common approach to frequency synthesis design for wireless communication is to design an analog-compensated fractional-N phase-locked loop (PLL). However, this technique suffers from lock time limitations, and inadequate fractional spur suppression, and falls short of third generation wireless standards. In this work, we propose three new delta-sigma PLL architectures to overcome the disadvantages of traditional PLLs. The first architecture addresses the spur reduction through the use of the sigma-delta modulator output as a dithering signal. The second architecture targets the speed and stability issue, as well as the power dissipation, by replacing the sigma-delta block with a pre-calculated ROM. The last architecture reduces both the power dissipation and the spur level through the implementation of a proposed tapering technique. The use of these architectures for closed-loop modulation is also examined.; The major advantages of these architectures include low-cost, low-power, and a fully monolithic solution. Throughout this work, low-power has been achieved by different architectural techniques that enable a tighter integration of the PLL'S loop components on a single chip, as well as a faster lock time.; Another pivotal block in wireless transceiver is the data converter. Data converters provide the two required bridges between the analog and digital worlds; as a result, data converters pose interesting and challenging tradeoffs that are relative to integration, process technology, and performance parameters.; Another goal of this thesis is to find methods for improving the performance (such as reducing power and energy consumption) of the analog-to-digital converter for wireless applications. A new analog-to-digital converter (ADC) architecture is devised. This architecture is memory-based: the last sample is used to predict the current one, resulting in both low-power dissipation and energy reduction. The low-power dissipation is a vital factor when we consider the chip reliability and integrity. The low-energy consumption is a critical factor when we consider battery operated devices. Moreover, the proposed memory-based ADC may be used to extend the attainable flash converter resolution by pre-calculating the most significant bits. |
