| Driven by the need for high-speed connectivity in short distances and the costs and difficulties of deploying cables, this thesis discusses the design of short-distance optical wireless data communications with the target speed of 1Gb/s. In addition to exploring the effect of individual components in this link, two blocks at the receiver side, the front-end transimpedance amplifier and the back-end detector, were designed and implemented and their performance summary are given below.; A transimpedance amplifier with differential dc-coupled photocurrent sensing was integrated in a standard 0.35 μm CMOS. It achieves 33kΩ transimpedance gain and a bandwidth of 255 MHz with a 2pF photodiode capacitance. This design exhibits 40dB power supply rejection ratio and an average input noise of 6.8pA/. Power dissipation is 30mW from a 3V supply. Also, an active dc photocurrent rejection circuit was included in this circuit to prevent the circuit output from saturation under intense background light.; A 1Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme was designed in a 0.25μm CMOS process. This chip is the first integrated implementation of an analog reduced state sequence detector. Pipelining structure and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200 Mb/s operation while simulation results indicate a speed of 1Gb/s. Power dissipation is 55mW from a 2.5V supply while occupying 0.78mm 2 of area. Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other PRS schemes such as dicode and PR4. |
