Design of CMOS ring oscillators with reduced phase noise

In this thesis a ring oscillator with stacked structure is presented and evaluated. The proposed circuit is investigated by studying its phase noise performance both in theory and practice. Analysis and prediction of performance improvement are presented and simulations show that the new structure achieves a 3 dBc/Hz reduction on phase noise. A total of four low-power fully-integrated voltage-controlled oscillators (YCOs) were designed in a 90 nm CMOS technology. Two of them are conventional inverter-based YCOs working at 433 MHz and 2.4 GHz, the other two are stacked inverter-based YCOs working at 433 MHz and 2.4 GHz respectively. Simulations show a 3 dBc/Hz phase noise reduction at 1 MHz offset with a power dissipation of less than 100 muW. These results demonstrate the feasibility of using the stacked structure in low power applications.