| A very low power FSK receiver has been designed for dual-purpose operation: deep space applications and general purpose baseband processing. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with an FFT based detection scheme to enable power consumption dramatically lower than a conventional implementation. Novel and power efficient algorithms are derived for frequency and timing acquisition and tracking. Extensive system level simulations and analytical derivations are used to find the optimal and critical system level parameters. A system/hardware co-design approach allows us to use a number of circuit level power reduction techniques while still meeting system level constraints. In particular, we designed a combination of fully-parallel and word-serial decimation stages to simultaneously optimize power consumption and silicon area. We also designed a very efficient FFT block that uses approximate arithmetic and pruning to greatly reduce overall complexity. Additional modules, such as DDFS and magnitude computation, have also been optimized in view of the targeted system parameters: signal to noise ratio and BER. The entire architecture has been made maximally flexible and power efficient by utilizing local clock gating and a simple inter-stage handshaking mechanism. The receiver has been implemented in 0.25mum CMOS technology, and takes up under 1 mm2. The power consumption is below 100muW for data rates below 20 kbps. Rates up to 2Mbps are supported. The worst case BER performance of the receiver is just 2.5 dB and 0.5 dB below that of the optimal uncoded non-coherent FSK receiver for space and terrestrial applications respectively at a BER of 10-5. |
